library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xianshi is
port(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9:IN STD_LOGIC;
clk:in std_logic;
q1,q2,q3,q4,q5,q6,q7,q8:out std_logic_vector(3 downto 0));
end;
architecture one of xianshi is
begin
process(clk,A0,A1,A2,A3,A4,A5,A6,A7,A8,A9)
VARIABLE P:STD_LOGIC_VECTOR(9 DOWNTO 0);
VARIABLE s:integer range 0 to 8;
VARIABLE t:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE w:STD_LOGIC_VECTOR(7 DOWNTO 0);
variable m1,m2,m3,m4,m5,m6,m7: std_logic_vector(3 downto 0);
begin
if clk'event and clk='1'then
p:=A0&A1&A2&A3&A4&A5&A6&A7&A8&A9;
if p>0 then s:=s+1;
if s>8 then s:=0;
end if;
case s is
when 0 =>w:="00000000";
when 1 =>w:="00000001";
when 2 =>w:="00000011";
when 3 =>w:="00000111";
when 4 =>w:="00001111";
when 5 =>w:="00011111";
when 6 =>w:="00111111";
when 7 =>w:="01111111";
when 8 =>w:="11111111";
when others =>null;
end case;
case p is
when "0000000001"=>t:="1001";
when "0000000010"=>t:="1000";
when "0000000100"=>t:="0111";
when "0000001000"=>t:="0110";
when "0000010000"=>t:="0101";
when "0000100000"=>t:="0100";
when "0001000000"=>t:="0011";
when "0010000000"=>t:="0010";
when "0100000000"=>t:="0001";
when "1000000000"=>t:="0000";
when others =>null;
end case;
if w="00000001" then q1<=t;
m1:=t;
elsif w="00000011" then q2<=m1;q1<=t;
m2:=m1;m1:=t;
elsif w="00000111" then q3<=m2;q2<=m1;q1<=t;
m3:=m2;m2:=m1;m1:=t;
elsif w="00001111" then q4<=m3;q3<=m2;q2<=m1;q1<=t;
m4:=m3;m3:=m2;m2:=m1;m1:=t;
elsif w="00011111" then q5<=m4;q4<=m3;q3<=m2;q2<=m1;q1<=t;
m5:=m4;m4:=m3;m3:=m2;m2:=m1;m1:=t;
elsif w="00111111" then q6<=m5;q5<=m4;q4<=m3;q3<=m2;q2<=m1;q1<=t;
m6:=m5;m5:=m4;m4:=m3;m3:=m2;m2:=m1;m1:=t;
elsif w="01111111" then q7<=m6;q6<=m5;q5<=m4;q4<=m3;q3<=m2;q2<=m1;q1<=t;
m7:=m6;m6:=m5;m5:=m4;m4:=m3;m3:=m2;m2:=m1;m1:=t;
elsif w="11111111" then q8<=m7;q7<=m6;q6<=m5;q5<=m4;q4<=m3;q3<=m2;q2<=m1;q1<=t;
end if;
end if;
end if;
end process;
end;
用verilog HDL编译发现很多错误，，希望有同学可以帮忙改下。。。 |
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