2# dqyubsh
这段是初始化GPIF模式
void GpifInit( void )
{
BYTE i;
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIF标志寄存器SEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
// 8051 doesn't have access to waveform memories 'til
// the part is in GPIF mode.
IFCONFIG = 0xCE;
// IFCLKSRC=1 , FIFOs executes on internal clk source
// xMHz=1 , 48MHz internal clk rate
// IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
// ASYNC=1 , master samples asynchronous
// GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
// IFCFG[1:0]=10, FX2 in GPIF master mode
GPIFABORT = 0xFF; // abort any waveforms pending
GPIFREADYCFG = InitData[ 0 ];
GPIFCTLCFG = InitData[ 1 ];
GPIFIDLECS = InitData[ 2 ];
GPIFIDLECTL = InitData[ 3 ];
GPIFWFSELECT = InitData[ 5 ];
GPIFREADYSTAT = InitData[ 6 ];
// use dual autopointer feature...
AUTOPTRSETUP = 0x07; // inc both pointers,
// ...warning: this introduces pdata hole(s)
// ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
// source
AUTOPTR1H = MSB( &WaveData );
AUTOPTR1L = LSB( &WaveData );
// destination
AUTOPTRH2 = 0xE4;
AUTOPTRL2 = 0x00;
// transfer
for ( i = 0x00; i < 128; i++ )
{
EXTAUTODAT2 = EXTAUTODAT1;
}
// Configure GPIF Address pins, output initial value,
PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
OEC = 0xFF; // and as outputs
PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
OEE |= 0x80; // and as output
// ...OR... tri-state GPIFADR[8:0] pins
// PORTCCFG = 0x00; // [7:0] as port I/O
// OEC = 0x00; // and as inputs
// PORTECFG &= 0x7F; // [8] as port I/O
// OEE &= 0x7F; // and as input
// GPIF address pins update when GPIFADRH/L written
SYNCDELAY; //
GPIFADRH = 0x00; // bits[7:1] always 0
SYNCDELAY; //
GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
// Configure GPIF FlowStates registers for Wave 0 of WaveData
FLOWSTATE = FlowStates[ 0 ];
FLOWLOGIC = FlowStates[ 1 ];
FLOWEQ0CTL = FlowStates[ 2 ];
FLOWEQ1CTL = FlowStates[ 3 ];
FLOWHOLDOFF = FlowStates[ 4 ];
FLOWSTB = FlowStates[ 5 ];
FLOWSTBEDGE = FlowStates[ 6 ];
FLOWSTBHPERIOD = FlowStates[ 7 ];
这段是读的功能：
if(in_enable) // if IN transfers are enabled
{
if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
{
if ( EXTFIFONOTEMPTY ) // if external FIFO is not empty
{
if ( !( EP68FIFO标志寄存器S & 0x01 ) ) // if EP6 FIFO is not full
{
if(enum_high_speed)
{
SYNCDELAY;
GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
SYNCDELAY;
GPIFTCB0 = 0x00;
SYNCDELAY;
}
else
{
SYNCDELAY;
GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20)
SYNCDELAY;
GPIFTCB0 = 0x20;
SYNCDELAY;
}
Setup_FLOWSTATE_Read(); // setup FLOWSTATE registers for FIFO Read operation
SYNCDELAY;
GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO
SYNCDELAY;
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
{
;
}
void Setup_FLOWSTATE_Read ( void )
{
FLOWSTATE = FlowStates[18]; // 1000 0011b - FSE=1, FS[2:0]=003
SYNCDELAY;
FLOWEQ0CTL = FlowStates[20]; // CTL1/CTL2 = 0 when flow condition equals zero (data flows)
SYNCDELAY;
FLOWEQ1CTL = FlowStates[21]; // CTL1/CTL2 = 1 when flow condition equals one (data does not flow)
SYNCDELAY;
}
}
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