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描述 This reference design demonstrates a validated and cost competitive power sequencing solution for an application processor or a high performance control platform. This design supports 5 different voltage rails, optimized with layout space of 12 mm × 12 mm. The design is also capable of adjusting delay time and re-configuring specific voltage level for each rail to fit different input capacitors and different processors' requirements.
特性- Validated power sequencing solution for application processors
- Correct power up/down sequence, even for uncontrolled power off at various load situations
- Power tree efficiency is maintained high both at heavy load and at a light load
- Small layout space of power supply: area smaller than 12 mm × 12 mm
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