增加对S3C2440的支持，2440的时钟计算公式、NAND操作和2410不太一样。 对于2440开发板，将FCLK设为400MHz，分频比为FCLK：HCLK：PCLK=1：4：8。 修改board/TX2440/TX2440.c中的board_init函数 /* S3C2440: Mpll,Upll = (2*m * Fin) / (p * 2^s)
* m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2
#define S3C2440_MPLL_400MHZ
((0x7f<<12)|(0x02<<4)|(0x01)) #define S3C2440_UPLL_48MHZ
((0x38<<12)|(0x02<<4)|(0x02)) #define S3C2440_CLKDIV
0x05
/* FCLK:HCLK:PCLK = 1:4:8 */ /* S3C2410: Mpll,Upll = (m * Fin) / (p * 2^s)
* m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2
#define S3C2410_MPLL_200MHZ
((0x5c<<12)|(0x04<<4)|(0x00)) #define S3C2410_UPLL_48MHZ
((0x28<<12)|(0x01<<4)|(0x02)) #define S3C2410_CLKDIV
0x03
/* FCLK:HCLK:PCLK = 1:2:4 */
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
/* set up the I/O ports */
gpio->GPACON = 0x007FFFFF;
gpio->GPBCON = 0x00044555;
gpio->GPBUP = 0x000007FF;
gpio->GPCCON = 0xAAAAAAAA;
gpio->GPCUP = 0x0000FFFF;
gpio->GPDCON = 0xAAAAAAAA;
gpio->GPDUP = 0x0000FFFF;
gpio->GPECON = 0xAAAAAAAA;
gpio->GPEUP = 0x0000FFFF;
gpio->GPFCON = 0x000055AA;
gpio->GPFUP = 0x000000FF;
gpio->GPGCON = 0xFF95FFBA;
gpio->GPGUP = 0x0000FFFF;
gpio->GPHCON = 0x002AFAAA;
gpio->GPHUP = 0x000007FF;
/*support both of S3C2410 and S3C2440*/
if ((gpio->GSTATUS1 == 0x32410000) || (gpio->GSTATUS1 == 0x32410002))
/*FCLK:HCLK:PCLK = 1:2:4*/
clk_power->CLKDIVN = S3C2410_CLKDIV;
/* change to asynchronous bus mod */
__asm__(
"mrc
p15, 0, r1, c1, c0, 0\n"
/* read ctrl register
*/
"orr
r1, r1, #0xc0000000\n"
/* Asynchronous
*/
"mcr
p15, 0, r1, c1, c0, 0\n"
/* write ctrl register
*/
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
clk_power->MPLLCON = S3C2410_MPLL_200MHZ;
/* some delay between MPLL and UPLL */
clk_power->UPLLCON = S3C2410_UPLL_48MHZ;
/* some delay between MPLL and UPLL */
/* arch number of SMDK2410-Board */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
/* FCLK:HCLK:PCLK = 1:4:8 */
clk_power->CLKDIVN = S3C2440_CLKDIV;
/* change to asynchronous bus mod */
__asm__(
"mrc
p15, 0, r1, c1, c0, 0\n"
/* read ctrl register
*/
"orr
r1, r1, #0xc0000000\n"
/* Asynchronous
*/
"mcr
p15, 0, r1, c1, c0, 0\n"
/* write ctrl register
*/
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
clk_power->MPLLCON = S3C2440_MPLL_400MHZ;
/* some delay between MPLL and UPLL */
clk_power->UPLLCON = S3C2440_UPLL_48MHZ;
/* some delay between MPLL and UPLL */
/* arch number of SMDK2440-Board */
gd->bd->bi_arch_number = MACH_TYPE_S3C2440;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x30000100;
在cpu/arm920t/s3c24X0/speed.c中修改： 在程序开头增加一行DECLARE_GLOBAL_DATA_PTR;，这样才可以使用gd变量 static ulong get_PLLCLK(int pllreg)
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
m = ((r & 0xFF000) >> 12) + 8;
p = ((r & 0x003F0) >> 4) + 2;
/* support both of S3C2410 and S3C2440 */
if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)
return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
return((CONFIG_SYS_CLK_FREQ * m * 2) / (p << s));
/* S3C2440 */
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