紧急help:这个verilog文件xst check syntax报错

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 楼主| edacsoft 发表于 2012-3-15 17:35 | 显示全部楼层 |阅读模式
网上下载的例子,应该是没有问题的。
verilog不熟悉。
ISE版本:11.5.
错误报告如下:
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 88 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 90 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 92 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 94 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 96 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 98 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 100 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 102 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 104 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 106 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 161 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 167 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 168 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 169 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 172 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 173 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 176 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 186 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 187 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 187 'cnt_clk_r' has not been declared
ERROR:HDLCompilers:28 - "HDL/sdram_ctrl.v" line 188 'cnt_clk_r' has not been declared



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 楼主| edacsoft 发表于 2012-3-15 17:40 | 显示全部楼层
原因找到了:
Before using an instance of a signal, array, parameter, etc., the instance must first be declared. The XST parser scans a Verilog file from beginning to end, so any usage must be preceded by the declaration of that instance.
晕死,XST跟其他综合器不一样.v中必须先声明再使用,真当是.c文件啊
GoldSunMonkey 发表于 2012-3-15 19:19 | 显示全部楼层
GoldSunMonkey 发表于 2012-3-15 19:19 | 显示全部楼层
我一看就知道未声明:)
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