3选1出问题了

library ieee;

use ieee.STD_LOGIC_1164.all;

library ieee;

use ieee.STD_LOGIC_ARITH.all;

library ieee;

use ieee.STD_LOGIC_UNSIGNED.all;



entity XGA_PLL is

port(

CLB : out std_logic;

CLK0 : out std_logic;

CLK1 : out std_logic;

CLK2 : out std_logic

);

end;



architecture XGA_PLL of XGA_PLL is

constant CLK0_CYCLE : TIME := 41.667 ns ;--24MHz

constant CLK1_CYCLE : TIME := 20.833 ns ;--48MHz

constant CLK2_CYCLE : TIME := 10.416 ns ;--96MHz



signal ICLK0 : std_logic;

signal ICLK1 : std_logic;

signal ICLK2 : std_logic;

signal ICLB : std_logic;



begin



process

begin

ICLK0 <= '1' ;wait for CLK0_CYCLE / 2;

ICLK0 <= '0' ;wait for CLK0_CYCLE / 2;

end process;

CLK0 <= ICLK0;



process

begin

ICLK1 <= '1' ;wait for CLK1_CYCLE / 2;

ICLK1 <= '0' ;wait for CLK1_CYCLE / 2;

end process;

CLK1 <= ICLK1;



process

begin

ICLK2 <= '1' ;wait for CLK2_CYCLE / 2;

ICLK2 <= '0' ;wait for CLK2_CYCLE / 2;

end process;

CLK2 <= ICLK2;



process

begin

ICLB <= '0' ;wait for CLK0_CYCLE * 16;

ICLB <= '1' ;wait;

end process;

CLB <= ICLB;



end;





library ieee;

use ieee.STD_LOGIC_1164.all;

library ieee;

use ieee.STD_LOGIC_ARITH.all;

library ieee;

use ieee.STD_LOGIC_UNSIGNED.all;





entity SSTC_TEST_TOP is

port(

-- CLB : in std_logic ;

-- CLK : in std_logic ;

FORMATCLK : out std_logic

-- locked : out std_logic

);

end;



architecture SSTC_TEST_TOP of SSTC_TEST_TOP is

signal ICLK : std_logic;

-- signal IQ : std_logic_vector(3 downto 0);

signal CLK_XGA1 : std_logic;

signal CLK_XGA2 : std_logic;

signal CLK_XGA3 : std_logic;

signal FORMATDAT : std_logic_vector(7 downto 0);

signal ICLB : std_logic;



component XGA_PLL

port (

CLB : out std_logic;

CLK0 : out std_logic;

CLK1 : out std_logic;

CLK2 : out std_logic

);

end component;



begin

C1: XGA_PLL

port map (

CLB => ICLB,

CLK0 => CLK_XGA1,

CLK1 => CLK_XGA2,

CLK2 => CLK_XGA3

);



process(ICLK)

begin

if ICLK'event and ICLK = '1' then

if ICLB = '0' then

FORMATCLK <= '0';

else 

case FORMATDAT(7 downto 0) is

when "00000000" => FORMATCLK <= CLK_XGA1;

when "00000001" => FORMATCLK <= CLK_XGA2;

when "00000010" => FORMATCLK <= CLK_XGA3;

when others => FORMATCLK <= '0';

end case;

end if;

end if;

end process;



process(ICLK)

begin

if ICLK'event and ICLK = '1' then

if ICLB = '0' then

FORMATDAT <= "00000000";

else FORMATDAT <= "00000010";

end if;

end if;

end process;



ICLK <= CLK_XGA1;



end SSTC_TEST_TOP;