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<br /><br />一段VHDL程序，有可能同时写同一信号出错。。寻求有效简单解决方法 <br />library ieee; <br />use ieee.std_logic_1164.all; <br />use ieee.std_logic_unsigned.all; <br /><br />entity main is <br /> generic(width:integer:=5); <br /> port( <br /> data:in std_logic_vector(width-1 downto 0); <br /> clk:in std_logic; <br /> write:in std_logic; <br /> pulse:out std_logic <br /> ); <br />end entity; <br /><br />architecture behave of main is <br />signal curcnt,cnt:std_logic_vector(width-1 downto 0); <br />begin <br /> process(data,clk,write) <br /> begin <br /> if write='1' then <br /> curcnt<=data; <br /> wb:='0'; <br /> end if; <br /> if clk'event and clk='1' then <br /> cnt<=cnt-1; <br /> if cnt=1 then <br /> pulse<='1'; <br /> cnt<=curcnt; <br /> curcnt<="00001"; --出问题就是这了。。可能同时写一个信号; <br /> <br /> else <br /> pulse<='0'; <br /> end if; <br /> end if; <br /> end process; <br />end behave; <br /> <br /> <br /> |
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