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1. Bachelor in Electrical/Electronic Engineering or higher <br />2. Very good knowledge of analog design rules, layout tools (cadence or laker), backend procedure (LVS, DRC, antenna, XOR), tapeout flow. 3. Familiar with digital P&R tools (Astro). Have knowledge on timing analysis, clock tree synthesis, power grid and power cap distribution, RC extraction <br /><br />4. More than 3 years experience with analog<br /><br />Location Beijing<br />hre@quintic.cn<br />http://www.quinticcorp.com/<br /> 相关链接:<a href='http://www.quinticcorp.com/'>http://www.quinticcorp.com/</a> |
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