报的错1g.vhd(9): near "select": expecting FUNCTION or PROCEDURE or IMPURE or PURE
上面这个是原题，然后我写的代码在下面，求各位大神施与援手啊，先谢谢了
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity g1 is
port(
clk: in std_logic;
select: in std_logic_vector(1 downto 0);
clkout: out std_logic
);
end entity g1;
architecture g1_1 of g1 is
signal state: std_logic_vector(20 downto 0);
begin
statep:process(clk) is
begin
if clk'event and clk='1' then
case select is
when "10"=>
if state<="00000000000000000011" then
state<=state+"00000000000000000001";
else
state<="00000000000000000000";
end if;
when "11"=>
if state<="00000000000000110001" then
state<=state+"00000000000000000001";
else
state<="00000000000000000000";
end if;
when "01"=>
if state<="00000000001111100111" then
state<=state+"00000000000000000001";
else
state<="00000000000000000000";
end if;
when "00"=>
if state<="11110100001000111111" then
state<=state+"00000000000000000001";
else
state<="00000000000000000000";
end if;
end case;
end if;
end process;
clkoutp:process(state,select) is
begin
case select is
when "10"=>
if state<="00000000000000000001" then
clkout<='1';
else
clkout<='0';
end if;
when "11"=>
if state<="00000000000000011000" then
clkout<='1';
else
clkout<='0';
end if;
when "01"=>
if state<="00000000000000010011" then
clkout<='1';
else
clkout<='0';
end if;
when "00"=>
if state="00000000000000000000" then
clkout<='1';
else
clkout<='0';
end if;
end case;
end process;
end architecture g1_1;
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