有人能帮我仿真一下这个VERILOG程序吗,非常级

只看该作者 · 2010-3-27 14:51

是一个5级CIC的程序，我因为第一次用QUARTUS2,所以仿真有些问题，有人能帮忙仿真一下波形给我参考吗
module CIC5(clk,x_in,clk2,y_out);
input clk;
input [7:0] x_in;
output[9:0]y_out;
output clk2;
reg clk2;
parameter hold=1'b0,sample=1'b1;
reg [1:0]state;
reg [4:0] counter;
reg [7:0]x;
wire [31:0]sxtx;
reg [31:0]int0,int1,int2,int3,int4;
reg[31:0]int2d1,int2d2, comb1,comb0;
reg[31:0]comb1d1,comb1d2,comb2;
reg[31:0]comb2d1,comb2d2,comb3;
reg[31:0]comb3d1,comb3d2,comb4;
reg[31:0]comb4d1,comb4d2,comb5;
always @(posedge clk)
begin:FSM
if (counter==24) begin
counter<=0;
state<=sample;
clk2<=1;
end
else begin
counter<=counter+1;
state<=hold;
clk2<=0;
end
end
assign sxtx = {{24{x[7]}},x};
always@(posedge clk)
begin:Int
x<=x_in;
int0<=int0+sxtx;
int1<=int1+int0;
int2<=int2+int1;
int3<=int3+int2;
int4<=int4+int3;
end
always@(posedge clk)
begin:comb
if (state == sample) begin
comb0 <= int4;
int2d1 <= comb0;
int2d2 <= int2d1;
comb1 <= comb0 - int2d2;
comb1d1 <= comb1;
comb1d2 <= comb1d1;
comb2 <= comb1 - comb1d2;
comb2d1 <= comb2;
comb2d2 <= comb2d1;
comb3 <= comb2 - comb2d2;
comb3d1<=comb3;
comb3d2<=comb3d1;
comb4<=comb3-comb3d2;
comb4d1<=comb4;
comb4d2<=comb4d1;
comb5<=comb4-comb4d2;
end
end
assign y_out=comb5[31:22];
如果有人弄好的话可以把波形发过来给我看一下,输入信号是幅值为127的阶跃信号
真的很急，谢谢了