中断，GPIO中data寄存器

只看该作者 · 2018-5-31 13:44

今天看到这两种写法，看不懂是怎么回事，来请教下

1、 IER |= M_INT3+M_INT4+M_INT1;
2、void SPWMDisable(void)
{
EALLOW;

Delay(200);

EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;

GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0; // Configure GPIO0 as EPWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0; // Configure GPIO1 as EPWM1B

Delay(200);
   // Enable an GPIO output on GPIO6, set it high
GpioDataRegs.GPADAT.bit.GPIO0 = 0; // Load output latch

Delay(200);

GpioDataRegs.GPADAT.bit.GPIO1 = 0; // Load output latch

Delay(200);

GpioDataRegs.GPADAT.bit.GPIO0 = 0; // Load output latch
GpioDataRegs.GPADAT.bit.GPIO1 = 0; // Load output latch

Delay(200);

GpioCtrlRegs.GPADIR.bit.GPIO0 = 1; // GPIO0 = output
GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; // GPIO1 = output

Delay(200);

EDIS;
}