proteL99SE中PCB进行DRC时出现如下错误信息怎么回事？

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aluesnow|

楼主 | 2009-3-8 02:52 | 只看该作者回帖奖励

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rc, Protel99SE, PCB, IO, TI

Protel Design System Design Rule Check
PCB File : DocumentsPCB1.PCB
Date     : 7-Mar-2009
Time     : 21:02:31

Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Prefered=10mil) (Disabled)(On the board )
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=20mil) (Prefered=20mil) (On the board )
Rule Violations :0

Processing Rule : Room Sheet1 (Region = (-260mil, 203.238mil, -259.989mil, 2328.188mil) (has footprint 0805 And Is part of Component class All Components And Is in component C1 )
   Violation between Component C1(49560mil,49700mil)  TopLayer and
                     Room Sheet1 (Region = (-260mil, 203.238mil, -259.989mil, 2328.188mil) (has footprint 0805 And Is part of Component class All Components And Is in component C1 )
Rule Violations :1

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=10mil) (On the board ),(On the board )
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (On the board ) )
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Rule Violations :0

Violations Detected : 1

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