日志
Xilinx AXI4 BRAM controller的应用
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这里用到了zynq、Axi BRAM Controller 和一个Block RAM.为了在板上验证，右边添加了一个从PortB读并显示在LED灯上的小模块 bram_led 。
bram_led的代码比较粗糙，具体的分频数可根据fclk_clk2的配置自行确定。这里设置的50M，因此led灯每1s会随读取到的bram内容变化一次。
附bram_led代码：
module bram_led
(
i_clk,
i_rst_n,
i_data,
o_addr,
o_led
);
parameter ADDR_WIDTH = 15;
parameter DATA_WIDTH = 32;
parameter COUNTER_WIDTH = 26;
parameter CLK_COUNTER = 50000000;
input wire i_clk;
input wire i_rst_n;
input wire [DATA_WIDTH - 1 :0] i_data;
output reg [ADDR_WIDTH - 1 : 0] o_addr;
output reg [7:0] o_led;
reg[COUNTER_WIDTH - 1 : 0] count;
always@(posedge i_clk or negedge i_rst_n) begin
if( !i_rst_n ) begin
count <= 26'h0;
end else if(count == CLK_COUNTER)begin
count <= 26'h0;
end else begin
count <= count + 4'h4;
end
end
always@(posedge i_clk or negedge i_rst_n) begin
if( !i_rst_n ) begin
o_addr <= 32'h00;
end else if(count == CLK_COUNTER) begin
o_addr <= o_addr + 4'd1;
end else begin
o_addr <= o_addr;
end
end
always@(posedge i_clk or negedge i_rst_n) begin
if( !i_rst_n ) begin
o_led <= 8'h00;
end else if(count == CLK_COUNTER) begin
o_led <= i_data;
end else begin
o_led <= o_led;
end
end
endmodule
AXI互联的逻辑是自动连线得到的。这样就可以通过zynq上的ARM硬核像访问内存一样访问BRAM了。
在address editor中可以配置axi bram controller的地址，这里直接采用默认的。
生成product 并且 建立hdl wapper之后，把enb直接拉到高电平，表示一直有效。
综合，实现，生成bit流并且导出到edk。可以看到我们刚才配置的bram-controller的地址：
建立一个helloword的standalone工程，输入以下初始化RAM的C代码：
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/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud rate 9600.
* PS7 UART (Zynq) is not initialized by this application, since
* bootrom/bsp configures it to baud rate 115200
*
* ------------------------------------------------
* | UART TYPE BAUD RATE |
* ------------------------------------------------
* uartns550 9600
* uartlite Configurable only in HW design
* ps7_uart 115200 (configured by bootrom/bsp)
*/
#include <stdio.h>
#include "platform.h"
#include "xil_io.h"//包含Xil_Out32函数
#include "sleep.h" //包含sleep函数
#define bram_base_addr 0x40000000 //基地址
int main()
{
u32 bram_offset_addr = 0x000000; //偏移地址
u32 bram_data = 0x00000001; //写入的数据
u32 data_read = 0;
while(1)
{
while(bram_offset_addr <= 0x1fff)
{
Xil_Out32(bram_base_addr + bram_offset_addr, bram_data);
bram_data = bram_data << 1;
if(bram_data == 0x100)
{
bram_data = 0x00000001;
}
bram_offset_addr += 0x04;
}
xil_printf("Write OK. Starting read...\r\n");
bram_offset_addr = 0;
while(bram_offset_addr <= 0x1ff)
{
data_read = Xil_In32(bram_base_addr + bram_offset_addr);
//xil_printf("0X%08X\r\n", data_read);
bram_offset_addr += 0x04;
}
while(1);
}
return 0;
}
