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module FIFO(clk, reset_n, data_in, read_n, write_n, data_out, full, empty);<br /> input clk;<br /> input reset_n;<br /> input [7:0] data_in;<br /> input read_n;<br /> input write_n;<br /> output [7:0] data_out;<br /> output full;<br /> output empty;<br /><br /> wire clk;<br /> wire reset_n;<br /> wire [7:0] data_in;<br /> wire read_n;<br /> wire write_n;<br /> wire full;<br /> wire empty;<br /> reg [7:0] data_out;<br /><br /> reg[7:0] fifo_mem[15:0]; //fifo存储体<br /> reg[3:0] counter; //计数器，表示fifo用了多少<br /> reg[3:0] rd_pointer; //fifo读指针<br /> reg[3:0] wr_pointer; //写指针<br /><br /> //满空状态标志<br /> assign #`del full=(counter==16)?1'b1:1'b0;<br /> assign #`del empty=(counter==0)?1'b1:1'b0;<br /><br /> //复位操作<br /> always@(reset_n)<br /> begin<br /> if(~reset_n)<br /> begin<br /> #`del;<br /> assign rd_pointer=4'b0;<br /> assign wr_pointer=4'b0;<br /> end<br /> else<br /> begin<br /> #`del;<br /> deassign rd_pointer;<br /> deassign wr_pointer;<br /> deassign counter;<br /> end<br /> end<br /><br /> //计数，读写功能<br /> always@(posedge clk)<br /> begin<br /> //读操作数，计数器递减<br /> if(write_n） ？？？这里为何只判断写使能无效就将计数器减1 <br /> begin<br /> counter<=#`del counter-1;<br /> end <br /> data_out<=#`del fifo_mem[rd_pointer];<br /> //如果读指针指向末尾，则返回<br /> if(rd_pointer==14) ？？？rd_pointer等于15时才复位吧<br /> rd_pointer<=#`del 4'b0;<br /> else<br /> rd_pointer<=#del rd_pointer+1;<br /><br /> if(~write_n)<br /> begin<br /> //检查是否溢出<br /> if(counter>=15)<br /> begin<br /> $display("\nerror at time %0t",$time);<br /> $display("fifo underflow\n");<br /> $stop<br /> end<br /> //写操作数，计数器加1<br /> if(read_n) ？？？这里为何只判断读使能无效就将计数器加1 <br /><br /> begin<br /> counter<=#`del counter+1;<br /> end<br /><br /> fifo_mem[wr_pointer]<=#`del data_in;<br /> //如果写指针指向末尾，则返回<br /> if(wr_pointer==14)<br /> wr_pointer<=#`del 4'b0;<br /> else<br /> wr_pointer<=#`del wr_pointer+1;<br /> end<br /><br /> end<br />endmodule<br /><br />好不容易手动把代码敲到ISE里面。觉得代码的逻辑太怪了，在读写标志递增时的条件判断感觉不对劲。 |
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楼主
