module FIFO(clk, reset_n, data_in, read_n, write_n, data_out, full, empty); input clk; input reset_n; input [7:0] data_in; input read_n; input write_n; output [7:0] data_out; output full; output empty;
wire clk; wire reset_n; wire [7:0] data_in; wire read_n; wire write_n; wire full; wire empty; reg [7:0] data_out;
reg[7:0] fifo_mem[15:0]; //fifo存储体 reg[3:0] counter; //计数器,表示fifo用了多少 reg[3:0] rd_pointer; //fifo读指针 reg[3:0] wr_pointer; //写指针
//满空状态标志 assign #`del full=(counter==16)?1'b1:1'b0; assign #`del empty=(counter==0)?1'b1:1'b0;
//复位操作 always@(reset_n) begin if(~reset_n) begin #`del; assign rd_pointer=4'b0; assign wr_pointer=4'b0; end else begin #`del; deassign rd_pointer; deassign wr_pointer; deassign counter; end end
//计数,读写功能 always@(posedge clk) begin //读操作数,计数器递减 if(write_n) ???这里为何只判断写使能无效就将计数器减1 begin counter<=#`del counter-1; end data_out<=#`del fifo_mem[rd_pointer]; //如果读指针指向末尾,则返回 if(rd_pointer==14) ???rd_pointer等于15时才复位吧 rd_pointer<=#`del 4'b0; else rd_pointer<=#del rd_pointer+1;
if(~write_n) begin //检查是否溢出 if(counter>=15) begin $display("\nerror at time %0t",$time); $display("fifo underflow\n"); $stop end //写操作数,计数器加1 if(read_n) ???这里为何只判断读使能无效就将计数器加1
begin counter<=#`del counter+1; end
fifo_mem[wr_pointer]<=#`del data_in; //如果写指针指向末尾,则返回 if(wr_pointer==14) wr_pointer<=#`del 4'b0; else wr_pointer<=#`del wr_pointer+1; end
end endmodule
好不容易手动把代码敲到ISE里面。觉得代码的逻辑太怪了,在读写标志递增时的条件判断感觉不对劲。 |