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//-----------------------------------------------------------------------------
//
// Title : driver_3k3_hipak_standard_tb
// Design : driver_3k3_2
// Author : Aldec, Inc
// Company : Aldec, Inc
//
//-----------------------------------------------------------------------------
//
// File : driver_3k3_hipak_standard_TB.v
// Generated : Sun Nov 4 16:25:14 2018
// From : E:\icecube2_workspace\3k3_driver\driver_3k3\aldec\driver_3k3_2\src\TestBench\driver_3k3_hipak_standard_TB_settings.txt
// By : tb_verilog.pl ver. ver 1.2s
//
//-----------------------------------------------------------------------------
//
// Description :
//
//-----------------------------------------------------------------------------
`timescale 1ns / 1ns
module driver_3k3_hipak_standard_tb;
//Internal signals declarations:
reg fault=0;
wire LED_TRIG;
wire IN_TD350;
wire fault_optical;
reg clk=0;
reg UVLO=0;
wire LED_FAULT;
reg IN=1;
always
#200 clk = ~clk;
initial
begin
UVLO = 1;
fault = 1;
IN = 1;
# 10000
IN = 0;
# 10000
IN = 1;
# 10000
IN = 0;
# 10000
IN = 1;
# 10000
IN = 0;
# 10000
IN = 1;
end
initial
begin
UVLO = 1;
# 5000;
UVLO = 0;
#10000;
UVLO = 1;
end
initial
begin
fault = 1;
#31000;
fault = 0;
#38000;
fault = 1;
end
// Unit Under Test port map
driver_3k3_hipak_standard UUT (
.fault(fault),
.LED_TRIG(LED_TRIG),
.IN_TD350(IN_TD350),
.fault_optical(fault_optical),
.clk(clk),
.UVLO(UVLO),
.LED_FAULT(LED_FAULT),
.IN(IN));
initial
$monitor($realtime,,"ps %h %h %h %h %h %h %h %h ",fault,LED_TRIG,IN_TD350,fault_optical,clk,UVLO,LED_FAULT,IN);
endmodule
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