vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" flow_led_vlg_tst
# vsim -gui "+altera" -l msim_transcript -do "flow_led_run_msim_rtl_verilog.do"
# Start time: 15:52:59 on Nov 23,2018
# ** Note: (vsim-3812) Design is being optimized...
#
# ** Fatal: Internal Error - vopt returned success but vsim could not find a design to simulate!. Please contact customer support for further assistance.
#
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./flow_led_run_msim_rtl_verilog.do PAUSED at line 40
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