代码如下：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY light IS
PORT (
clk : IN STD_LOGIC;
led : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END light;
ARCHITECTURE trans OF light IS
signal sel :std_LOGIC_VECTOR(2 downto 0);
signal num :std_LOGIC_VECTOR(7 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1')then
sel<=sel+'1';
if(sel<="111") then
sel<="000";
num<=num+'1';
end if;
end if;
end process;
process (num)
begin
case num is
when "00000000"=>led<="10000000";
when "00000001"=>led<="01000000";
when "00000010"=>led<="00100000";
when "00000011"=>led<="00010000";
when "00000100"=>led<="00001000";
when "00000101"=>led<="00000100";
when "00000110"=>led<="00000010";
when "00000111"=>led<="00000001";
when others =>null;
end case;
end process;
end trans;
谁帮我看看啊！ |
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楼主
