reg[15:0] pixcel_buf[15:0];//16*16 bit refresh tft screen data buffer<br /><br />Error: NETLIST:001 Behavioral HDL is not supported. Module vga has behavioral code in FILE E:vga_lcdmini2440verilogVGAh<br /><br />这可是 verilog的标准语法啊。<br /><br />altera就没问题。 |
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