21ic问答首页 - HC32F460芯片片内温度使用HRC时钟源,读取温度失败
HC32F460芯片片内温度使用HRC时钟源,读取温度失败
HC32F460芯片系统时钟使用HRC后,片内温度使用HRC时钟源,读取温度失败
代码如下,希望各位大佬提供一下帮助,谢谢谢谢
__WEAKDEF void BSP_CLK_Init(void)
{
//stc_clock_xtal_init_t stcXtalInit;
stc_clock_pll_init_t stcMpllInit;
//GPIO_AnalogCmd(BSP_XTAL_PORT, BSP_XTAL_PIN, ENABLE);
//(void)CLK_XtalStructInit(&stcXtalInit);
(void)CLK_PLLStructInit(&stcMpllInit);
/* Set bus clk div. */
CLK_SetClockDiv(CLK_BUS_CLK_ALL, (
CLK_HCLK_DIV1 | // 200MHz
CLK_EXCLK_DIV2 | // 100MHz
CLK_PCLK0_DIV1 | // 200MHz
CLK_PCLK1_DIV2 | // 100MHz
CLK_PCLK2_DIV4 | // 50MHz
CLK_PCLK3_DIV4 | // 50MHz
CLK_PCLK4_DIV2 // 100MHz
));
/* TODO. 使能HRC并等待稳定 */
(void)CLK_HrcCmd(ENABLE);
while (SET != CLK_GetStableStatus(CLK_STB_FLAG_HRC)) {
; // 等待HRC稳定
}
/* MPLL config (HRC / pllmDiv * plln / PllpDiv = 200M). */
stcMpllInit.PLLCFGR = 0UL;
stcMpllInit.PLLCFGR_f.PLLM = 2UL - 1UL;
stcMpllInit.PLLCFGR_f.PLLN = 50UL - 1UL;
stcMpllInit.PLLCFGR_f.PLLP = 2UL - 1UL;
stcMpllInit.PLLCFGR_f.PLLQ = 2UL - 1UL;
stcMpllInit.PLLCFGR_f.PLLR = 2UL - 1UL;
stcMpllInit.u8PLLState = CLK_PLL_ON;
stcMpllInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_HRC;//TODO:改内部时钟 16MHz
(void)CLK_PLLInit(&stcMpllInit);
/* Wait MPLL ready. */
while (SET != CLK_GetStableStatus(CLK_STB_FLAG_PLL)) {
;
}
/* sram init include read/write wait cycle setting */
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
SRAM_SetWaitCycle((SRAM_SRAM12 | SRAM_SRAM3 | SRAM_SRAMR), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
/* flash read wait cycle setting */
(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
/* 3 cycles for 126MHz ~ 200MHz */
GPIO_SetReadWaitCycle(GPIO_RD_WAIT3);
/* Switch driver ability */
(void)PWC_HighSpeedToHighPerformance();
/* Switch system clock source to MPLL. */
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
/* Reset cache ram */
EFM_CacheRamReset(ENABLE);
EFM_CacheRamReset(DISABLE);
/* Enable cache */
EFM_CacheCmd(ENABLE);
}
片内温度初始化代码如下
#define OTS_CLK_SEL (OTS_CLK_HRC)
/* OTS parameters, slope K and offset M. Different chip, different parameters. */
#define OTS_HRC_K (3002.59F)
#define OTS_HRC_M (27.92F)
/* Timeout value. */
#define OTS_TIMEOUT_VAL (10000U)
/**
* @brief OTS initialization configuration.
* @param None
* @retval None
*/
static void OtsInitConfig(void)
{
stc_ots_init_t stcOTSInit;
(void)OTS_StructInit(&stcOTSInit);
stcOTSInit.u16ClockSrc = OTS_CLK_SEL;
stcOTSInit.f32SlopeK = OTS_HRC_K;
stcOTSInit.f32OffsetM = OTS_HRC_M;
/* 1. Enable OTS peripheral clock. */
FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_OTS, ENABLE);
/* 2. Initialize OTS. */
(void)OTS_Init(&stcOTSInit);
}
/**
* @brief OTS clock configuration.
* @param None
* @retval None
*/
static void OtsClockConfig(void)
{
/* 1. Enable HRC for OTS. */
(void)CLK_HrcCmd(ENABLE);
/* 2. Enable XTAL32 when clock source of OTS is HRC. */
(void)CLK_Xtal32Cmd(ENABLE);
/* Enable LRC for OTS. */
(void)CLK_LrcCmd(ENABLE);
}
代码如下,希望各位大佬提供一下帮助,谢谢谢谢
__WEAKDEF void BSP_CLK_Init(void)
{
//stc_clock_xtal_init_t stcXtalInit;
stc_clock_pll_init_t stcMpllInit;
//GPIO_AnalogCmd(BSP_XTAL_PORT, BSP_XTAL_PIN, ENABLE);
//(void)CLK_XtalStructInit(&stcXtalInit);
(void)CLK_PLLStructInit(&stcMpllInit);
/* Set bus clk div. */
CLK_SetClockDiv(CLK_BUS_CLK_ALL, (
CLK_HCLK_DIV1 | // 200MHz
CLK_EXCLK_DIV2 | // 100MHz
CLK_PCLK0_DIV1 | // 200MHz
CLK_PCLK1_DIV2 | // 100MHz
CLK_PCLK2_DIV4 | // 50MHz
CLK_PCLK3_DIV4 | // 50MHz
CLK_PCLK4_DIV2 // 100MHz
));
/* TODO. 使能HRC并等待稳定 */
(void)CLK_HrcCmd(ENABLE);
while (SET != CLK_GetStableStatus(CLK_STB_FLAG_HRC)) {
; // 等待HRC稳定
}
/* MPLL config (HRC / pllmDiv * plln / PllpDiv = 200M). */
stcMpllInit.PLLCFGR = 0UL;
stcMpllInit.PLLCFGR_f.PLLM = 2UL - 1UL;
stcMpllInit.PLLCFGR_f.PLLN = 50UL - 1UL;
stcMpllInit.PLLCFGR_f.PLLP = 2UL - 1UL;
stcMpllInit.PLLCFGR_f.PLLQ = 2UL - 1UL;
stcMpllInit.PLLCFGR_f.PLLR = 2UL - 1UL;
stcMpllInit.u8PLLState = CLK_PLL_ON;
stcMpllInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_HRC;//TODO:改内部时钟 16MHz
(void)CLK_PLLInit(&stcMpllInit);
/* Wait MPLL ready. */
while (SET != CLK_GetStableStatus(CLK_STB_FLAG_PLL)) {
;
}
/* sram init include read/write wait cycle setting */
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
SRAM_SetWaitCycle((SRAM_SRAM12 | SRAM_SRAM3 | SRAM_SRAMR), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
/* flash read wait cycle setting */
(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
/* 3 cycles for 126MHz ~ 200MHz */
GPIO_SetReadWaitCycle(GPIO_RD_WAIT3);
/* Switch driver ability */
(void)PWC_HighSpeedToHighPerformance();
/* Switch system clock source to MPLL. */
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
/* Reset cache ram */
EFM_CacheRamReset(ENABLE);
EFM_CacheRamReset(DISABLE);
/* Enable cache */
EFM_CacheCmd(ENABLE);
}
片内温度初始化代码如下
#define OTS_CLK_SEL (OTS_CLK_HRC)
/* OTS parameters, slope K and offset M. Different chip, different parameters. */
#define OTS_HRC_K (3002.59F)
#define OTS_HRC_M (27.92F)
/* Timeout value. */
#define OTS_TIMEOUT_VAL (10000U)
/**
* @brief OTS initialization configuration.
* @param None
* @retval None
*/
static void OtsInitConfig(void)
{
stc_ots_init_t stcOTSInit;
(void)OTS_StructInit(&stcOTSInit);
stcOTSInit.u16ClockSrc = OTS_CLK_SEL;
stcOTSInit.f32SlopeK = OTS_HRC_K;
stcOTSInit.f32OffsetM = OTS_HRC_M;
/* 1. Enable OTS peripheral clock. */
FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_OTS, ENABLE);
/* 2. Initialize OTS. */
(void)OTS_Init(&stcOTSInit);
}
/**
* @brief OTS clock configuration.
* @param None
* @retval None
*/
static void OtsClockConfig(void)
{
/* 1. Enable HRC for OTS. */
(void)CLK_HrcCmd(ENABLE);
/* 2. Enable XTAL32 when clock source of OTS is HRC. */
(void)CLK_Xtal32Cmd(ENABLE);
/* Enable LRC for OTS. */
(void)CLK_LrcCmd(ENABLE);
}
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