1、要进入Jtag,RTCK【p1.26】在上电时需要为低电平。 “P1.26 RTCK Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bi-directional pin with internal pullup. LOW on this pin while RESET is LOW enables pins P1.31:26 to operate as a Debug port after reset.
Important: LOW on pin P1.26 while RESET is LOW enables pins P1.31:26 to operate as a Debug port after reset.”