When memory loading is heavy, there is chance that IPU DI can't access memory on time, then such error will appear.
You can add the followed register setting in uboot file flash_header.S, it will enable AXI cache and give IPU high priority to access AXI bus. This is the default setting for 3.10 BSP.
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, 0x020e0010, 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, 0x020e0018, 0x007F007F
DATA 4, 0x020e001c, 0x007F007F
For example in 3.0.35 uboot, u-boot-2009.08\board\freescale\mx6q_sabresd\flash_header.S
- dcd_hdr: .word 0x40a002D2 /* Tag=0xD2, Len=83*8 + 4 + 4, Ver=0x40 */
- write_dcd_cmd: .word 0x049c02CC /* Tag=0xCC, Len=83*8 + 4, Param=0x04 */
+ dcd_hdr: .word 0x40b802D2 /* Tag=0xD2, Len=86*8 + 4 + 4, Ver=0x40 */
+ write_dcd_cmd: .word 0x04b402CC /* Tag=0xCC, Len=86*8 + 4, Param=0x04 */
... ...
MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+ MXC_DCD_ITEM(84, 0x020e0010, 0xF00000CF)
+ MXC_DCD_ITEM(85, 0x020e0018, 0x007F007F)
+ MXC_DCD_ITEM(86, 0x020e001c, 0x007F007F) |
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