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下面是我例程带的启动代码，哪个高手帮我改一下（能进入FIQ中断）<br />;/*****************************************************************************<br />;* startup.s: startup file for NXP LPC24** Family Microprocessors<br />;*<br />;* Copyright(C) 2006, NXP Semiconductor<br />;* All rights reserved.<br />;*<br />;* History<br />;* 2006.09.01 ver 1.00 Prelimnary version, first Release<br />;*****************************************************************************/<br /><br />;/*<br />; * The STARTUP.S code is executed after CPU Reset. This file may be <br />; * translated with the following SET symbols. In uVision these SET <br />; * symbols are entered under Options - ASM - Define.<br />; *<br />; * REMAP: when set the startup code initializes the register MEMMAP <br />; * which overwrites the settings of the CPU configuration pins. The <br />; * startup and interrupt vectors are remapped from:<br />; * 0x00000000 default setting (not remapped)<br />; * 0x40000000 when RAM_MODE is used<br />; *<br />; * RAM_MODE: when set the device is configured for code execution<br />; * from on-chip RAM starting at address 0x40000000. <br />; */<br /><br />; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs<br /><br />Mode_USR DEFINE 0x10<br />Mode_FIQ DEFINE 0x11<br />Mode_IRQ DEFINE 0x12<br />Mode_SVC DEFINE 0x13<br />Mode_ABT DEFINE 0x17<br />Mode_UND DEFINE 0x1B<br />Mode_SYS DEFINE 0x1F<br /><br />I_Bit DEFINE 0x80 ; when I bit is set, IRQ is disabled<br />F_Bit DEFINE 0x40 ; when F bit is set, FIQ is disabled<br /><br />; Exception Vectors<br />; Mapped to Address 0.<br />; Absolute addressing mode must be used.<br />; Dummy Handlers are implemented as infinite loops which can be modified.<br /><br /> PROGRAM ?RESET<br /> COMMON INTVEC:CODE(3)<br /> PUBLIC __program_start<br /> EXTERN Reset_Handler, Undef_Handler, SWI_Handler, PAbt_Handler, DAbt_Handler, FIQ_Handler<br /> CODE32 ; Always ARM mode after reset<br /><br />__program_start<br /> LDR PC, =Reset_Handler<br /> LDR PC, =Undef_Handler<br /> LDR PC, =SWI_Handler<br /> LDR PC, =PAbt_Handler<br /> LDR PC, =DAbt_Handler<br /> B .<br /> LDR PC, [PC, #-0x0120] ; Vector from VicVectAddr<br /> LDR PC, =FIQ_Handler<br /><br /> LTORG<br /> ENDMOD<br /><br />; Reset Handler<br /><br /> MODULE ?CSTARTUP<br /> RSEG IRQ_STACK:DATA(3)<br /> RSEG FIQ_STACK:DATA(3)<br /> RSEG SVC_STACK:DATA(3)<br /> RSEG ABT_STACK:DATA(3)<br /> RSEG UND_STACK:DATA(3)<br /> RSEG CSTACK:DATA(3)<br /> RSEG ICODE:CODE(3)<br /> PUBLIC Reset_Handler, Undef_Handler, SWI_Handler, PAbt_Handler, DAbt_Handler, FIQ_Handler<br /> EXTERN ?main<br /> CODE32<br /><br />Reset_Handler<br /><br />; Enter Undefined Instruction Mode and set its Stack Pointer<br /> MSR CPSR_c, #Mode_UND|I_Bit|F_Bit<br /> LDR SP, =SFE(UND_STACK)&0xFFFFFFF8<br /><br />; Enter Abort Mode and set its Stack Pointer<br /> MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit<br /> LDR SP, =SFE(ABT_STACK)&0xFFFFFFF8<br /><br />; Enter FIQ Mode and set its Stack Pointer<br /> MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit<br /> LDR SP, =SFE(FIQ_STACK)&0xFFFFFFF8<br /><br />; Enter IRQ Mode and set its Stack Pointer<br /> MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit<br /> LDR SP, =SFE(IRQ_STACK)&0xFFFFFFF8<br /><br />; Enter Supervisor Mode and set its Stack Pointer<br /> MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit<br /> LDR SP, =SFE(SVC_STACK)&0xFFFFFFF8<br /><br />; Enter User Mode and set its Stack Pointer<br /> MSR CPSR_c, #Mode_USR<br /> LDR SP, =SFE(CSTACK)&0xFFFFFFF8<br /><br />; Enter the C code<br /><br /> LDR R0, =?main<br /> BX R0<br /> B .<br /><br />Undef_Handler<br />SWI_Handler<br />PAbt_Handler<br />DAbt_Handler<br />FIQ_Handler<br /> B .<br /><br /> LTORG<br /> ENDMOD<br /> END<br />
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