请阿南兄介绍此段文字的出处,参考整篇**才能更加准确

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 楼主| 阿南 发表于 2008-3-22 11:04 | 显示全部楼层 |阅读模式
原句如下:<br />from&nbsp;simple&nbsp;memory&nbsp;blocks&nbsp;with&nbsp;a&nbsp;flat&nbsp;address&nbsp;map,&nbsp;to&nbsp;systems&nbsp;using&nbsp;any&nbsp;or&nbsp;all&nbsp;of&nbsp;the&nbsp;following&nbsp;to&nbsp;optimize&nbsp;their&nbsp;use&nbsp;of&nbsp;memory&nbsp;resources:<br /><br />谢谢兄弟们,帮忙翻译一下.哈哈<br /><br />
joywyc 发表于 2008-3-23 02:08 | 显示全部楼层

应该从专业角度来进行翻译——

simple&nbsp;memory&nbsp;blocks&nbsp;with&nbsp;a&nbsp;flat&nbsp;address&nbsp;map&nbsp;应该译成:<br />&nbsp;&nbsp;(带有)平坦寻址映射的单一存储块<br />其中:memory&nbsp;blocks&nbsp;——&nbsp;存储块;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;a&nbsp;flat&nbsp;address&nbsp;——&nbsp;平坦寻址;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;map&nbsp;——&nbsp;映射。<br />这是32位μCP存储器系统的一种寻址模式(4GB寻址),不同于过去的20位μCP存储器系统,段址+基址的寻址模式。<br />
平常人 发表于 2008-3-24 22:28 | 显示全部楼层

俺也从专业角度来说说

先抄录原文于此,以便参考:from&nbsp;simple&nbsp;memory&nbsp;blocks&nbsp;with&nbsp;a&nbsp;flat&nbsp;address&nbsp;map,&nbsp;to&nbsp;systems&nbsp;using&nbsp;any&nbsp;or&nbsp;all&nbsp;of&nbsp;the&nbsp;following&nbsp;to&nbsp;optimize&nbsp;their&nbsp;use&nbsp;of&nbsp;memory&nbsp;resources:<br /><br />首先,存储器的组织有很多种,常见的有两种,一是线性寻址结构,即文中所说的flat&nbsp;address,所以也经常有人用linear&nbsp;addressing表述,此处用flat是为了有别于下面的层次型结构。二是层次型的页式或段式结构,常见的说法有page&nbsp;addressing或segment&nbsp;addressing,这种层次型的结构便于使用MMU管理或使用较短的寻址指令访问较大的地址空间。除此之外还有其他一些组织结构。<br /><br />搞清楚flat&nbsp;address的意义,理解文中的simple&nbsp;memory&nbsp;block就很容易了,这里的simple肯定是相对随后要谈到的复杂存储结构(systems&nbsp;using&nbsp;any&nbsp;or&nbsp;all&nbsp;of&nbsp;the&nbsp;following&nbsp;使用下述任一种或全部结构的系统),而这个复杂存储结构肯定是我上面谈到的层次型结构。<br /><br />至于此段文字的翻译,我认为4楼的译文基本正确,只是flat译成linear更好:<br />“从具有线性存储映射的简单存储体,到。。。。。”
 楼主| 阿南 发表于 2008-3-22 11:11 | 显示全部楼层

查了一下,理解的不知是否正确

从简单平板地址映射的存储区,到....<br /><br /><br />大伙指点下,帮忙给个准确些的<br />
 楼主| 阿南 发表于 2008-3-22 11:19 | 显示全部楼层

又查了一下:从单一平坦寻址映射的存储空间,到...

  
123654789 发表于 2008-3-22 11:36 | 显示全部楼层

我来了 !

from&nbsp;simple&nbsp;memory&nbsp;blocks&nbsp;with&nbsp;a&nbsp;flat&nbsp;address&nbsp;map,&nbsp;to&nbsp;systems&nbsp;using&nbsp;any&nbsp;or&nbsp;all&nbsp;of&nbsp;the&nbsp;following&nbsp;to&nbsp;optimize&nbsp;their&nbsp;use&nbsp;of&nbsp;memory&nbsp;resources:<br /><br />with是一个介词,意思是带有<br />blocks&nbsp;with&nbsp;address&nbsp;map,&nbsp;构成介宾短语<br />简单缩写就是blocks&nbsp;with&nbsp;address&nbsp;map<br />address&nbsp;map包含在memory&nbsp;blocks里面<br />整个句子翻译就是<br />从简单平坦地址图的存储区,到系统,<br />使用下面的一部分或者全部的来优化存储体资源的使用<br /><br />我没有查字典的翻译<br />如果能翻译正确,说明我还年轻,**力好<br />否则,我人老珠黄了
 楼主| 阿南 发表于 2008-3-22 14:45 | 显示全部楼层

呵呵,123果然是高手,谢谢

这是ARM官方的文档,介绍的是ARM存储系统<br /><br /><br /><br />
dld2 发表于 2008-3-22 14:53 | 显示全部楼层

翻译要信、达、雅,太难!

好在多数时候工程师只要理解意思就好了。
 楼主| 阿南 发表于 2008-3-24 12:05 | 显示全部楼层

哈哈,谢谢joywyc

  
iC921 发表于 2008-3-27 20:47 | 显示全部楼层

借机学点东西:所谓平坦寻扯,是什么意思?

反正是“a&nbsp;flat&nbsp;address”。<br /><br />a&nbsp;flat&nbsp;address&nbsp;——&nbsp;平坦寻址;<br /><br />至于此段文字的翻译,我认为4楼的译文基本正确,只是flat译成linear更好:<br />“从具有线性存储映射的简单存储体,到。。。。。”<br />
宇宙飞船 发表于 2008-3-27 21:25 | 显示全部楼层

from ....,to ,在此就译成:因为所以的意思。

from&nbsp;simple&nbsp;memory&nbsp;blocks&nbsp;with&nbsp;a&nbsp;flat&nbsp;address&nbsp;map,&nbsp;to&nbsp;systems&nbsp;using&nbsp;any&nbsp;or&nbsp;all&nbsp;of&nbsp;the&nbsp;following&nbsp;to&nbsp;optimize&nbsp;their&nbsp;use&nbsp;of&nbsp;memory&nbsp;resources:<br />由于带有一个单一平坦(线性)地址映射的储存块,系统可以使用任何或全部跟踪以优化它们的内存资源的使用。
iC921 发表于 2008-3-27 21:30 | 显示全部楼层

好你个飞船,我都以为你消失了!

这个盘要是再跌,责任整个归你!!
平常人 发表于 2008-3-27 21:41 | 显示全部楼层

请阿南兄介绍此段文字的出处,参考整篇**才能更加准确

此文是否可从ARM网站下载?
宇宙飞船 发表于 2008-3-27 21:45 | 显示全部楼层

恭喜IC921任英语角的版主!

最近项目紧,立下军令状,不成功便成仁了。<br />估计一年内也不会有多少时间发贴。等俺这个项目做好了,到时俺一定会来的。到时俺还想竟争做这个坛子的版主呢!
123654789 发表于 2008-3-27 21:48 | 显示全部楼层

宇宙飞船 错了

following&nbsp;是&nbsp;下面&nbsp;的意思(下面某某东西)相当于一个名词<br /><br />不是&nbsp;跟随&nbsp;的意思<br /><br />follow&nbsp;及物动词&nbsp;跟踪
iC921 发表于 2008-3-27 22:41 | 显示全部楼层

哈哈,飞船受到挑战了!

123mm是正确的,而且any应当译作“任一”更准确,因为后面跟有“all”。<br /><br /><br />你想干完活再回来争当版主,我才不信,象你这样的人才,不可能让你有空的,因此,你只能经常偷空来灌水。<br /><br /><br /><br />to&nbsp;平常人,我代你呼叫阿南去~<br /><br />
 楼主| 阿南 发表于 2008-3-28 12:15 | 显示全部楼层

对不起,让大伙久等了

这是ADS安装后自带的在线手册《ARM&nbsp;Architecture&nbsp;Reference&nbsp;Manual》的第11章&nbsp;Introduction&nbsp;to&nbsp;Memory&nbsp;and&nbsp;System&nbsp;Architectures<br />原文如:<br /><br /><br /><br />11&nbsp;&nbsp;Introduction&nbsp;to&nbsp;Memory&nbsp;and&nbsp;System&nbsp;Architectures<br />This&nbsp;chapter&nbsp;provides&nbsp;a&nbsp;high-level&nbsp;overview&nbsp;of&nbsp;memory&nbsp;and&nbsp;system&nbsp;architectures.&nbsp;It&nbsp;contains&nbsp;the&nbsp;following&nbsp;sections:<br />about&nbsp;the&nbsp;memory&nbsp;system<br />system-level&nbsp;issues.<br />11.1&nbsp;&nbsp;About&nbsp;the&nbsp;memory&nbsp;system<br /><font color=#0000FF>ARM&nbsp;processors&nbsp;are&nbsp;used&nbsp;in&nbsp;a&nbsp;wide&nbsp;range&nbsp;of&nbsp;embedded&nbsp;systems&nbsp;and&nbsp;other&nbsp;applications.&nbsp;The&nbsp;memory&nbsp;system&nbsp;requirements&nbsp;of&nbsp;these&nbsp;applications&nbsp;vary&nbsp;considerably,&nbsp;from&nbsp;simple&nbsp;memory&nbsp;blocks&nbsp;with&nbsp;a&nbsp;flat&nbsp;address&nbsp;map,&nbsp;to&nbsp;systems&nbsp;using&nbsp;any&nbsp;or&nbsp;all&nbsp;of&nbsp;the&nbsp;following&nbsp;to&nbsp;optimize&nbsp;their&nbsp;use&nbsp;of&nbsp;memory&nbsp;resources:<br /> <li>multiple&nbsp;types&nbsp;of&nbsp;memory</li><br /> <li>caches  </li><br /> <li>write&nbsp;buffers </li><br /> <li>virtual&nbsp;memory&nbsp;and&nbsp;other&nbsp;memory&nbsp;remapping&nbsp;techniques.</li></font><br />The&nbsp;range&nbsp;of&nbsp;memory-mapped&nbsp;I/O&nbsp;devices&nbsp;that&nbsp;can&nbsp;be&nbsp;used&nbsp;adds&nbsp;further&nbsp;to&nbsp;the&nbsp;variety&nbsp;of&nbsp;systems&nbsp;based&nbsp;on&nbsp;ARM&nbsp;processors.&nbsp;<br />Most&nbsp;systems&nbsp;need&nbsp;to&nbsp;initialize&nbsp;and&nbsp;control&nbsp;their&nbsp;memory&nbsp;system&nbsp;facilities&nbsp;in&nbsp;various&nbsp;ways,&nbsp;such&nbsp;as:<br />Enabling&nbsp;a&nbsp;cache,&nbsp;to&nbsp;ensure&nbsp;that&nbsp;its&nbsp;performance&nbsp;benefits&nbsp;are&nbsp;realized.<br />Setting&nbsp;up&nbsp;the&nbsp;virtual-to-physical&nbsp;address&nbsp;mapping&nbsp;for&nbsp;a&nbsp;virtual&nbsp;memory&nbsp;system.<br />Restricting&nbsp;access&nbsp;to&nbsp;memory&nbsp;regions.<br />Ensuring&nbsp;that&nbsp;the&nbsp;correct&nbsp;accesses&nbsp;to&nbsp;memory-mapped&nbsp;I/O&nbsp;devices&nbsp;occur,&nbsp;and&nbsp;that&nbsp;they&nbsp;occur&nbsp;at&nbsp;the&nbsp;correct&nbsp;times.&nbsp;(This&nbsp;usually&nbsp;happens&nbsp;automatically&nbsp;in&nbsp;the&nbsp;simplest&nbsp;memory&nbsp;systems,&nbsp;but&nbsp;caches&nbsp;and&nbsp;other&nbsp;facilities&nbsp;in&nbsp;more&nbsp;complex&nbsp;systems&nbsp;can&nbsp;interfere&nbsp;with&nbsp;it.)<br />The&nbsp;standard&nbsp;way&nbsp;to&nbsp;perform&nbsp;memory&nbsp;system&nbsp;control&nbsp;in&nbsp;ARM-based&nbsp;systems&nbsp;is&nbsp;to&nbsp;use&nbsp;coprocessor&nbsp;15&nbsp;(CP15),&nbsp;which&nbsp;is&nbsp;also&nbsp;known&nbsp;as&nbsp;the&nbsp;System&nbsp;Control&nbsp;coprocessor.&nbsp;Chapter&nbsp;12&nbsp;The&nbsp;System&nbsp;Control&nbsp;Coprocessor&nbsp;provides&nbsp;a&nbsp;top-level&nbsp;overview&nbsp;of&nbsp;this&nbsp;coprocessor.<br />The&nbsp;rest&nbsp;of&nbsp;Part&nbsp;B&nbsp;(Chapter&nbsp;13&nbsp;through&nbsp;Chapter&nbsp;16)&nbsp;describes&nbsp;standardized&nbsp;ways&nbsp;to&nbsp;perform&nbsp;a&nbsp;variety&nbsp;of&nbsp;memory&nbsp;system&nbsp;control&nbsp;operations&nbsp;using&nbsp;CP15:<br />Chapter&nbsp;13&nbsp;Memory&nbsp;Management&nbsp;Unit<br />Describes&nbsp;a&nbsp;sophisticated&nbsp;system&nbsp;to&nbsp;control&nbsp;virtual-to-physical&nbsp;address&nbsp;mapping,&nbsp;access&nbsp;permissions&nbsp;to&nbsp;memory,&nbsp;and&nbsp;other&nbsp;memory&nbsp;attributes,&nbsp;based&nbsp;on&nbsp;the&nbsp;use&nbsp;of&nbsp;a&nbsp;Memory&nbsp;Management&nbsp;Unit&nbsp;(MMU).<br />Chapter&nbsp;14&nbsp;Protection&nbsp;Unit<br />Describes&nbsp;a&nbsp;simpler&nbsp;Protection&nbsp;Unit&nbsp;system&nbsp;which&nbsp;is&nbsp;suitable&nbsp;for&nbsp;many&nbsp;applications&nbsp;which&nbsp;do&nbsp;not&nbsp;require&nbsp;the&nbsp;full&nbsp;facilities&nbsp;provided&nbsp;by&nbsp;the&nbsp;MMU&nbsp;memory&nbsp;system.<br />Chapter&nbsp;15&nbsp;Caches&nbsp;and&nbsp;Write&nbsp;Buffers<br />Describes&nbsp;facilities&nbsp;to&nbsp;control&nbsp;caches&nbsp;and&nbsp;write&nbsp;buffers.&nbsp;These&nbsp;are&nbsp;common&nbsp;to&nbsp;the&nbsp;MMU&nbsp;and&nbsp;Protection&nbsp;Unit&nbsp;systems<br />Chapter&nbsp;16&nbsp;Fast&nbsp;Context&nbsp;Switch&nbsp;Extension<br />Describes&nbsp;the&nbsp;Fast&nbsp;Context&nbsp;Switch&nbsp;Extension,&nbsp;which&nbsp;facilitates&nbsp;fast&nbsp;switching&nbsp;between&nbsp;up&nbsp;to&nbsp;128&nbsp;processes&nbsp;executing&nbsp;in&nbsp;separate&nbsp;process&nbsp;blocks,&nbsp;each&nbsp;of&nbsp;size&nbsp;up&nbsp;to&nbsp;32MB.<br />Note<br />Because&nbsp;of&nbsp;the&nbsp;wide&nbsp;variety&nbsp;of&nbsp;systems&nbsp;based&nbsp;on&nbsp;ARM&nbsp;processors,&nbsp;all&nbsp;functionality&nbsp;described&nbsp;in&nbsp;Part&nbsp;B&nbsp;might&nbsp;be&nbsp;inappropriate&nbsp;to&nbsp;any&nbsp;given&nbsp;system.&nbsp;Furthermore,&nbsp;some&nbsp;ARM&nbsp;processors&nbsp;have&nbsp;implemented&nbsp;functions&nbsp;in&nbsp;a&nbsp;different&nbsp;manner&nbsp;to&nbsp;the&nbsp;one&nbsp;described&nbsp;here.&nbsp;Because&nbsp;of&nbsp;this,&nbsp;the&nbsp;datasheet&nbsp;or&nbsp;Technical&nbsp;Reference&nbsp;Manual&nbsp;for&nbsp;a&nbsp;particular&nbsp;ARM&nbsp;processor&nbsp;is&nbsp;the&nbsp;definitive&nbsp;source&nbsp;for&nbsp;its&nbsp;memory&nbsp;and&nbsp;system&nbsp;control&nbsp;facilities.<br />Part&nbsp;B&nbsp;therefore&nbsp;does&nbsp;not&nbsp;attempt&nbsp;to&nbsp;specify&nbsp;absolute&nbsp;requirements&nbsp;on&nbsp;the&nbsp;functionality&nbsp;of&nbsp;the&nbsp;System&nbsp;Control&nbsp;coprocessor&nbsp;or&nbsp;other&nbsp;memory&nbsp;system&nbsp;components.&nbsp;Instead,&nbsp;it&nbsp;contains&nbsp;guidelines&nbsp;which,&nbsp;if&nbsp;followed:&nbsp;<br />?mean&nbsp;that&nbsp;the&nbsp;system&nbsp;is&nbsp;more&nbsp;likely&nbsp;to&nbsp;be&nbsp;compatible&nbsp;with&nbsp;existing&nbsp;and&nbsp;future&nbsp;ARM&nbsp;software.<br />?probably&nbsp;make&nbsp;it&nbsp;easier&nbsp;to&nbsp;port&nbsp;incompatible&nbsp;software&nbsp;to&nbsp;the&nbsp;system.<br />In&nbsp;order&nbsp;to&nbsp;provide&nbsp;an&nbsp;adequate&nbsp;description&nbsp;of&nbsp;the&nbsp;range&nbsp;of&nbsp;memory&nbsp;and&nbsp;system&nbsp;facilities&nbsp;on&nbsp;existing&nbsp;ARM&nbsp;implementations,&nbsp;Part&nbsp;B&nbsp;describes&nbsp;a&nbsp;number&nbsp;of&nbsp;options&nbsp;that&nbsp;will&nbsp;not&nbsp;be&nbsp;used&nbsp;on&nbsp;new&nbsp;ARM&nbsp;implementations.&nbsp;For&nbsp;information&nbsp;on&nbsp;the&nbsp;rules&nbsp;that&nbsp;must&nbsp;be&nbsp;followed&nbsp;by&nbsp;new&nbsp;implementations&nbsp;of&nbsp;the&nbsp;memory&nbsp;and&nbsp;system&nbsp;architectures,&nbsp;contact&nbsp;ARM&nbsp;Ltd.&nbsp;<br />The&nbsp;fact&nbsp;that&nbsp;Part&nbsp;B&nbsp;describes&nbsp;a&nbsp;broad&nbsp;range&nbsp;of&nbsp;facilities,&nbsp;many&nbsp;of&nbsp;which&nbsp;are&nbsp;used&nbsp;only&nbsp;on&nbsp;some&nbsp;existing&nbsp;ARM&nbsp;implementations,&nbsp;also&nbsp;means&nbsp;that&nbsp;architecture&nbsp;version&nbsp;numbers&nbsp;for&nbsp;the&nbsp;memory&nbsp;and&nbsp;system&nbsp;architectures&nbsp;would&nbsp;not&nbsp;be&nbsp;helpful&nbsp;or&nbsp;descriptive.&nbsp;They&nbsp;are&nbsp;therefore&nbsp;not&nbsp;used.<br />11.2&nbsp;&nbsp;System-level&nbsp;issues<br />This&nbsp;section&nbsp;lists&nbsp;a&nbsp;number&nbsp;of&nbsp;general&nbsp;and&nbsp;operating-system&nbsp;issues&nbsp;that&nbsp;the&nbsp;system&nbsp;designer&nbsp;needs&nbsp;to&nbsp;address&nbsp;when&nbsp;using&nbsp;an&nbsp;ARM&nbsp;processor.<br />11.2.1&nbsp;&nbsp;Memory&nbsp;systems,&nbsp;write&nbsp;buffers&nbsp;and&nbsp;caches<br />ARM&nbsp;processors&nbsp;and&nbsp;software&nbsp;are&nbsp;designed&nbsp;to&nbsp;be&nbsp;connected&nbsp;to&nbsp;a&nbsp;byte-addressed&nbsp;memory.&nbsp;Word&nbsp;and&nbsp;halfword&nbsp;accesses&nbsp;to&nbsp;the&nbsp;memory&nbsp;ignore&nbsp;the&nbsp;alignment&nbsp;of&nbsp;the&nbsp;address&nbsp;and&nbsp;access&nbsp;the&nbsp;naturally-aligned&nbsp;value&nbsp;that&nbsp;is&nbsp;addressed&nbsp;(so&nbsp;a&nbsp;memory&nbsp;access&nbsp;ignores&nbsp;address&nbsp;bits&nbsp;0&nbsp;and&nbsp;1&nbsp;for&nbsp;word&nbsp;access,&nbsp;and&nbsp;ignores&nbsp;bit&nbsp;0&nbsp;for&nbsp;halfword&nbsp;accesses).&nbsp;The&nbsp;endianness&nbsp;of&nbsp;the&nbsp;ARM&nbsp;processor&nbsp;should&nbsp;normally&nbsp;match&nbsp;that&nbsp;of&nbsp;the&nbsp;memory&nbsp;system,&nbsp;or&nbsp;be&nbsp;configured&nbsp;to&nbsp;match&nbsp;it&nbsp;before&nbsp;any&nbsp;non-word&nbsp;accesses&nbsp;occur&nbsp;(when&nbsp;the&nbsp;endianness&nbsp;is&nbsp;configurable&nbsp;and&nbsp;CP15&nbsp;is&nbsp;implemented,&nbsp;bit[7]&nbsp;of&nbsp;CP15&nbsp;register&nbsp;1&nbsp;controls&nbsp;the&nbsp;endianness).<br />Memory&nbsp;that&nbsp;is&nbsp;used&nbsp;to&nbsp;hold&nbsp;programs&nbsp;and&nbsp;data&nbsp;should&nbsp;be&nbsp;marked&nbsp;as&nbsp;follows:<br />稭ain&nbsp;(RAM)&nbsp;memory&nbsp;is&nbsp;normally&nbsp;set&nbsp;as&nbsp;cachable&nbsp;and&nbsp;bufferable.<br />稲OM&nbsp;memory&nbsp;is&nbsp;normally&nbsp;set&nbsp;as&nbsp;cachable,&nbsp;and&nbsp;should&nbsp;be&nbsp;marked&nbsp;as&nbsp;read&nbsp;only,&nbsp;so&nbsp;the&nbsp;bufferable&nbsp;attribute&nbsp;is&nbsp;not&nbsp;used&nbsp;and&nbsp;should&nbsp;be&nbsp;1.<br />Write&nbsp;buffers<br />Some&nbsp;ARM&nbsp;implementations&nbsp;incorporate&nbsp;a&nbsp;merging&nbsp;write&nbsp;buffer&nbsp;that&nbsp;subsumes&nbsp;multiple&nbsp;writes&nbsp;to&nbsp;the&nbsp;same&nbsp;location&nbsp;into&nbsp;a&nbsp;single&nbsp;write&nbsp;to&nbsp;main&nbsp;memory.&nbsp;Furthermore,&nbsp;some&nbsp;write&nbsp;buffers&nbsp;re-order&nbsp;writes,&nbsp;so&nbsp;that&nbsp;writes&nbsp;are&nbsp;issued&nbsp;to&nbsp;memory&nbsp;in&nbsp;a&nbsp;different&nbsp;order&nbsp;to&nbsp;the&nbsp;order&nbsp;in&nbsp;which&nbsp;they&nbsp;are&nbsp;issued&nbsp;by&nbsp;the&nbsp;processor.&nbsp;Therefore,&nbsp;I/O&nbsp;locations&nbsp;should&nbsp;not&nbsp;normally&nbsp;be&nbsp;marked&nbsp;as&nbsp;bufferable,&nbsp;to&nbsp;ensure&nbsp;all&nbsp;writes&nbsp;are&nbsp;issued&nbsp;to&nbsp;the&nbsp;I/O&nbsp;device&nbsp;in&nbsp;the&nbsp;correct&nbsp;order.<br />For&nbsp;writes&nbsp;to&nbsp;bufferable&nbsp;areas&nbsp;of&nbsp;memory,&nbsp;memory&nbsp;aborts&nbsp;can&nbsp;only&nbsp;be&nbsp;signaled&nbsp;to&nbsp;the&nbsp;processor&nbsp;as&nbsp;a&nbsp;result&nbsp;of&nbsp;conditions&nbsp;that&nbsp;are&nbsp;detectable&nbsp;at&nbsp;the&nbsp;time&nbsp;the&nbsp;data&nbsp;is&nbsp;placed&nbsp;in&nbsp;the&nbsp;write&nbsp;buffer.&nbsp;Conditions&nbsp;that&nbsp;can&nbsp;only&nbsp;be&nbsp;detected&nbsp;when&nbsp;the&nbsp;data&nbsp;is&nbsp;later&nbsp;written&nbsp;to&nbsp;main&nbsp;memory&nbsp;(such&nbsp;as&nbsp;a&nbsp;parity&nbsp;error&nbsp;from&nbsp;main&nbsp;memory)&nbsp;must&nbsp;be&nbsp;handled&nbsp;by&nbsp;other&nbsp;methods&nbsp;(typically&nbsp;by&nbsp;raising&nbsp;an&nbsp;interrupt).<br />Caches<br />Frame&nbsp;buffers&nbsp;can&nbsp;be&nbsp;cachable,&nbsp;but&nbsp;frame&nbsp;buffers&nbsp;on&nbsp;writeback&nbsp;cache&nbsp;implementations&nbsp;must&nbsp;be&nbsp;copied&nbsp;back&nbsp;to&nbsp;memory&nbsp;after&nbsp;the&nbsp;frame&nbsp;buffer&nbsp;has&nbsp;been&nbsp;updated.&nbsp;Frame&nbsp;buffers&nbsp;can&nbsp;be&nbsp;bufferable,&nbsp;but&nbsp;again&nbsp;the&nbsp;write&nbsp;buffer&nbsp;must&nbsp;be&nbsp;written&nbsp;back&nbsp;to&nbsp;memory&nbsp;after&nbsp;the&nbsp;frame&nbsp;buffer&nbsp;has&nbsp;been&nbsp;updated.<br />ARM&nbsp;processors&nbsp;do&nbsp;not&nbsp;normally&nbsp;support&nbsp;cache&nbsp;coherence&nbsp;between&nbsp;the&nbsp;ARM&nbsp;and&nbsp;other&nbsp;system&nbsp;bus&nbsp;masters.&nbsp;Bus&nbsp;snooping&nbsp;is&nbsp;not&nbsp;supported.&nbsp;If&nbsp;memory&nbsp;data&nbsp;is&nbsp;to&nbsp;be&nbsp;shared&nbsp;between&nbsp;multiple&nbsp;bus&nbsp;masters&nbsp;without&nbsp;taking&nbsp;special&nbsp;software&nbsp;measures&nbsp;to&nbsp;ensure&nbsp;coherency,&nbsp;then&nbsp;the&nbsp;data&nbsp;must&nbsp;be&nbsp;mapped&nbsp;as:&nbsp;<br />穟ncachable&nbsp;to&nbsp;ensure&nbsp;that&nbsp;all&nbsp;reads&nbsp;access&nbsp;main&nbsp;memory<br />穟nbufferable&nbsp;to&nbsp;ensure&nbsp;that&nbsp;all&nbsp;write&nbsp;access&nbsp;main&nbsp;memory.<br />Alternatively,&nbsp;using&nbsp;software,&nbsp;you&nbsp;can&nbsp;manage&nbsp;the&nbsp;coherence&nbsp;of&nbsp;data&nbsp;buffers&nbsp;that&nbsp;are&nbsp;read&nbsp;or&nbsp;written&nbsp;by&nbsp;another&nbsp;bus&nbsp;master&nbsp;by:<br />穋leaning&nbsp;data&nbsp;from&nbsp;writeback&nbsp;caches&nbsp;and&nbsp;write&nbsp;buffers&nbsp;to&nbsp;memory&nbsp;when&nbsp;the&nbsp;processor&nbsp;has&nbsp;written&nbsp;to&nbsp;the&nbsp;data&nbsp;buffer&nbsp;and&nbsp;before&nbsp;the&nbsp;other&nbsp;bus&nbsp;master&nbsp;reads&nbsp;the&nbsp;buffer<br />穎lushing&nbsp;relevant&nbsp;data&nbsp;from&nbsp;caches&nbsp;when&nbsp;the&nbsp;buffer&nbsp;is&nbsp;being&nbsp;read&nbsp;after&nbsp;the&nbsp;other&nbsp;bus&nbsp;master&nbsp;has&nbsp;written&nbsp;the&nbsp;buffer.&nbsp;<br />You&nbsp;can&nbsp;use&nbsp;an爑ncached,&nbsp;unbuffered&nbsp;semaphore&nbsp;to&nbsp;maintain&nbsp;synchronization&nbsp;between&nbsp;multiple&nbsp;bus&nbsp;masters&nbsp;(see燬emaphores).&nbsp;<br />For&nbsp;implementations&nbsp;with&nbsp;writeback&nbsp;caches,&nbsp;all&nbsp;dirty&nbsp;cache&nbsp;data&nbsp;must&nbsp;be&nbsp;written&nbsp;back&nbsp;before&nbsp;any&nbsp;alterations&nbsp;are&nbsp;made&nbsp;to&nbsp;the&nbsp;MMU&nbsp;page&nbsp;tables,&nbsp;to&nbsp;ensure&nbsp;that&nbsp;cache&nbsp;line&nbsp;write&nbsp;back&nbsp;can&nbsp;use&nbsp;the&nbsp;page&nbsp;tables&nbsp;to&nbsp;form&nbsp;the&nbsp;correct&nbsp;physical&nbsp;address&nbsp;for&nbsp;the&nbsp;transfer.<br />You&nbsp;can&nbsp;index&nbsp;caches&nbsp;using&nbsp;either&nbsp;virtual&nbsp;or&nbsp;physical&nbsp;addresses.&nbsp;Physical&nbsp;pages&nbsp;must&nbsp;only&nbsp;be&nbsp;mapped&nbsp;into&nbsp;a&nbsp;single&nbsp;virtual&nbsp;page,&nbsp;otherwise&nbsp;the&nbsp;result&nbsp;is&nbsp;UNPREDICTABLE.&nbsp;ARM&nbsp;processors&nbsp;do&nbsp;not&nbsp;normally&nbsp;provide&nbsp;coherence&nbsp;between&nbsp;multiple&nbsp;virtual&nbsp;copies&nbsp;of&nbsp;a&nbsp;single&nbsp;physical&nbsp;page.<br />Some&nbsp;ARM&nbsp;implementations&nbsp;support&nbsp;separate&nbsp;instruction&nbsp;and&nbsp;data&nbsp;caches.&nbsp;Coherence&nbsp;between&nbsp;the&nbsp;data&nbsp;and&nbsp;instruction&nbsp;caches&nbsp;is&nbsp;not&nbsp;necessarily&nbsp;maintained&nbsp;in&nbsp;hardware,&nbsp;so&nbsp;if&nbsp;the&nbsp;instruction&nbsp;stream&nbsp;is&nbsp;written,&nbsp;the&nbsp;instruction&nbsp;cache&nbsp;and&nbsp;data&nbsp;cache&nbsp;must&nbsp;be&nbsp;made&nbsp;coherent.&nbsp;This&nbsp;can&nbsp;entail:<br />穋leaning&nbsp;the&nbsp;data&nbsp;cache&nbsp;(storing&nbsp;dirty&nbsp;data&nbsp;to&nbsp;memory)<br />穌raining&nbsp;the&nbsp;write&nbsp;buffer&nbsp;(completing&nbsp;all&nbsp;buffered&nbsp;writes)<br />穎lushing&nbsp;the&nbsp;instruction&nbsp;cache.<br />Instruction&nbsp;and&nbsp;data&nbsp;memory&nbsp;incoherence&nbsp;occurs&nbsp;after&nbsp;a&nbsp;program&nbsp;has&nbsp;been&nbsp;loaded&nbsp;(and&nbsp;therefore&nbsp;treated&nbsp;as&nbsp;data)&nbsp;and&nbsp;is&nbsp;about&nbsp;to&nbsp;be&nbsp;executed.&nbsp;It&nbsp;also&nbsp;occurs&nbsp;if&nbsp;self-modifying&nbsp;code&nbsp;is&nbsp;used&nbsp;or&nbsp;generated.<br />11.2.2&nbsp;&nbsp;Interrupts<br />ARM&nbsp;processors&nbsp;implement&nbsp;fast&nbsp;and&nbsp;normal&nbsp;levels&nbsp;of&nbsp;interrupt.&nbsp;Both&nbsp;interrupts&nbsp;are&nbsp;signaled&nbsp;externally,&nbsp;and&nbsp;many&nbsp;implementations&nbsp;synchronize&nbsp;interrupts&nbsp;before&nbsp;an&nbsp;exception&nbsp;is&nbsp;raised.&nbsp;<br />Fast&nbsp;interrupt&nbsp;request&nbsp;(FIQ)<br />Disables&nbsp;subsequent&nbsp;normal&nbsp;and&nbsp;fast&nbsp;interrupts&nbsp;by&nbsp;setting&nbsp;the&nbsp;I&nbsp;and&nbsp;F&nbsp;bits&nbsp;in&nbsp;the&nbsp;CPSR.<br />Normal&nbsp;interrupt&nbsp;request&nbsp;(IRQ)<br />Disables&nbsp;&nbsp;subsequent&nbsp;normal&nbsp;interrupts&nbsp;by&nbsp;setting&nbsp;the營&nbsp;bit&nbsp;in&nbsp;the&nbsp;CPSR.<br />For&nbsp;more&nbsp;information,&nbsp;see&nbsp;Exceptions.<br />Canceling&nbsp;interrupts<br />It&nbsp;is&nbsp;the&nbsp;responsibility&nbsp;of&nbsp;software&nbsp;(the&nbsp;interrupt&nbsp;handler)&nbsp;to&nbsp;ensure&nbsp;that&nbsp;the&nbsp;cause&nbsp;of&nbsp;an爄nterrupt&nbsp;is&nbsp;canceled&nbsp;(no&nbsp;longer&nbsp;signaled&nbsp;to&nbsp;the&nbsp;processor)&nbsp;before&nbsp;interrupts&nbsp;are&nbsp;re-enabled&nbsp;(by&nbsp;clearing&nbsp;the&nbsp;I&nbsp;and/or&nbsp;F&nbsp;bit&nbsp;in&nbsp;the&nbsp;CPSR).&nbsp;Interrupts&nbsp;can&nbsp;be&nbsp;canceled&nbsp;with&nbsp;any&nbsp;instruction&nbsp;that&nbsp;might&nbsp;make&nbsp;an&nbsp;external&nbsp;data&nbsp;bus&nbsp;access,&nbsp;meaning&nbsp;any&nbsp;load&nbsp;or&nbsp;store,&nbsp;a爏wap,&nbsp;or&nbsp;any&nbsp;coprocessor&nbsp;instruction.&nbsp;<br />Canceling&nbsp;an&nbsp;interrupt&nbsp;via&nbsp;an&nbsp;instruction&nbsp;fetch&nbsp;is&nbsp;UNPREDICTABLE.&nbsp;<br />Canceling&nbsp;an&nbsp;interrupt&nbsp;with&nbsp;a&nbsp;load&nbsp;multiple&nbsp;that&nbsp;restores&nbsp;the&nbsp;CPSR&nbsp;and&nbsp;re-enables&nbsp;interrupts&nbsp;is&nbsp;UNPREDICTABLE.<br />Devices&nbsp;that&nbsp;do&nbsp;not&nbsp;instantaneously&nbsp;cancel&nbsp;an&nbsp;interrupt&nbsp;(that&nbsp;is,&nbsp;they&nbsp;do&nbsp;not&nbsp;cancel&nbsp;the爄nterrupt&nbsp;before&nbsp;letting&nbsp;the&nbsp;access&nbsp;complete)&nbsp;must&nbsp;be&nbsp;probed&nbsp;by&nbsp;software&nbsp;to&nbsp;ensure&nbsp;that&nbsp;interrupts&nbsp;have&nbsp;been&nbsp;canceled&nbsp;before&nbsp;interrupts&nbsp;are&nbsp;re-enabled.&nbsp;This&nbsp;allows&nbsp;a燿evice&nbsp;connected&nbsp;to&nbsp;a爎emote&nbsp;I/O&nbsp;bus&nbsp;to&nbsp;operate&nbsp;correctly.<br />11.2.3&nbsp;&nbsp;Semaphores<br />The&nbsp;Swap&nbsp;and&nbsp;Swap&nbsp;Byte&nbsp;instructions&nbsp;have&nbsp;predictable&nbsp;behavior&nbsp;when&nbsp;used&nbsp;in&nbsp;two&nbsp;ways:<br />稴ystems&nbsp;with&nbsp;multiple&nbsp;bus&nbsp;masters&nbsp;that&nbsp;use&nbsp;the&nbsp;Swap&nbsp;instructions&nbsp;to&nbsp;implement&nbsp;semaphores&nbsp;to&nbsp;control&nbsp;interaction&nbsp;between&nbsp;different&nbsp;bus&nbsp;masters.&nbsp;<br />In&nbsp;this&nbsp;case,&nbsp;the&nbsp;semaphores&nbsp;must&nbsp;be&nbsp;placed&nbsp;in&nbsp;an&nbsp;uncached&nbsp;and&nbsp;unbufferable&nbsp;region&nbsp;of&nbsp;memory.&nbsp;The&nbsp;Swap&nbsp;instruction&nbsp;then&nbsp;causes&nbsp;a&nbsp;(locked)&nbsp;read-write&nbsp;bus&nbsp;transaction.&nbsp;<br />This爐ype&nbsp;of&nbsp;semaphore&nbsp;can&nbsp;be&nbsp;externally&nbsp;aborted.<br />稴ystems&nbsp;with&nbsp;multiple&nbsp;threads&nbsp;running&nbsp;on&nbsp;a&nbsp;uniprocessor&nbsp;that&nbsp;use&nbsp;the&nbsp;Swap&nbsp;instructions&nbsp;to&nbsp;implement&nbsp;semaphores&nbsp;to&nbsp;control&nbsp;interaction&nbsp;of&nbsp;the&nbsp;threads.<br />In&nbsp;this&nbsp;case,&nbsp;the&nbsp;semaphores&nbsp;can&nbsp;be&nbsp;placed&nbsp;in&nbsp;a&nbsp;cached&nbsp;and&nbsp;bufferable&nbsp;region&nbsp;of&nbsp;memory,&nbsp;and&nbsp;a&nbsp;(locked)&nbsp;read-write&nbsp;bus&nbsp;transaction&nbsp;might&nbsp;or&nbsp;might&nbsp;not&nbsp;occur.&nbsp;The&nbsp;Swap&nbsp;and&nbsp;Swap&nbsp;Byte&nbsp;instructions&nbsp;are&nbsp;likely&nbsp;to&nbsp;have&nbsp;better&nbsp;performance&nbsp;on&nbsp;such&nbsp;a&nbsp;system&nbsp;than&nbsp;they&nbsp;do&nbsp;on&nbsp;a&nbsp;system&nbsp;with&nbsp;multiple&nbsp;bus&nbsp;masters&nbsp;(as&nbsp;described&nbsp;above).&nbsp;<br />This&nbsp;type&nbsp;of&nbsp;semaphore&nbsp;has&nbsp;UNPREDICTABLE&nbsp;behavior&nbsp;if&nbsp;it&nbsp;is&nbsp;externally&nbsp;aborted.<br />Semaphores&nbsp;placed&nbsp;in&nbsp;uncachable/bufferable&nbsp;memory&nbsp;regions&nbsp;have&nbsp;UNPREDICTABLE&nbsp;results.&nbsp;Semaphores&nbsp;placed&nbsp;in&nbsp;cachable/unbufferable&nbsp;memory&nbsp;regions&nbsp;have&nbsp;UNPREDICTABLE&nbsp;results.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 楼主| 阿南 发表于 2008-3-28 12:21 | 显示全部楼层

想念 飞船兄,哈哈

  
alice84 发表于 2008-3-28 12:43 | 显示全部楼层

走私一下

  
平常人 发表于 2008-3-28 23:15 | 显示全部楼层

从具有线性存储映射的简单存储体,到。。。。。

根据阿南兄发表的整个原文看,我之前的理解是完全正确的:<br /><br /><b>ARM&nbsp;processors&nbsp;are&nbsp;used&nbsp;in&nbsp;a&nbsp;wide&nbsp;range&nbsp;of&nbsp;embedded&nbsp;systems&nbsp;and&nbsp;other&nbsp;applications.&nbsp;The&nbsp;memory&nbsp;system&nbsp;requirements&nbsp;of&nbsp;these&nbsp;applications&nbsp;vary&nbsp;considerably,&nbsp;<u>from&nbsp;simple&nbsp;memory&nbsp;blocks&nbsp;with&nbsp;a&nbsp;flat&nbsp;address&nbsp;map,&nbsp;to&nbsp;systems&nbsp;using&nbsp;any&nbsp;or&nbsp;all&nbsp;of&nbsp;the&nbsp;following&nbsp;to&nbsp;optimize&nbsp;their&nbsp;use&nbsp;of&nbsp;memory&nbsp;resources</u>:<br />multiple&nbsp;types&nbsp;of&nbsp;memory<br />caches<br />write&nbsp;buffers<br />virtual&nbsp;memory&nbsp;and&nbsp;other&nbsp;memory&nbsp;remapping&nbsp;techniques.</b><br /><br /><font color=#0000FF>从具有线性存储映射的简单存储体,到为优化存储器资源而使用以下任一项或所有手段的系统</font>
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