刚学习FPGA，在网上看到了RAM的读写，自己也写了一个。写的时候少写一个数据，而且读出数据开头老是XXXX，求大神指教。
以下是程序：
module test(D2_datain,
D2_dataout,
D2_addr,
IS62_WE,
IS62_RD,
D2CS_N,
D2XINT1,
fpga_clk,
);
inout [15:0] D2_datain;
inout [15:0] D2_dataout;
input [7:0] D2_addr;
input IS62_WE;
input IS62_RD;
input D2CS_N;
input fpga_clk;
output D2XINT1;
reg [15:0] memblk [0:255];
reg [7:0] ramaddr1;
// reg [7:0] ramaddr2;
reg [15:0] rd_data1;
wire system_clk;
IBUFG clock(.I(fpga_clk), .O(system_clk)); //全局时钟使用Bufg缓冲
parameter count_12K = 12'd3906; //50M分频为12.8K
reg [11:0] cnt_1s = 12'd0; //分频计数器
always@(posedge system_clk)
if(cnt_1s < count_12K)
cnt_1s <= cnt_1s + 1'd1;
else
cnt_1s <= 12'd0;
reg dspclk=1'b0;
always @(posedge system_clk)
if(cnt_1s == count_12K) begin
dspclk= ~dspclk;
end
assign D2XINT1=dspclk;
assign D2_dataout=(IS62_RD==1'b0 && D2CS_N==1'b0) ? rd_data1 : 16'bz;
always @( posedge system_clk)
if(D2CS_N==0)
begin
if(IS62_WE==1'b0)
begin
ramaddr1<=D2_addr;
memblk[ramaddr1] <=D2_datain;
end
else if(IS62_RD==1'b0)
begin
ramaddr1<=D2_addr;
rd_data1<=memblk[ramaddr1];
end
end
endmodule
然后是激励程序
reg [7:0] ADDR1=8'b0;
reg [7:0] ADDR2=8'b0;
reg [15:0] data_t=16'b1;
reg [15:0] data_c=16'b0;
reg [15:0] DataR[0:64];
assign D2_datain=data_c;
initial forever #10 fpga_clk=!fpga_clk;
initial begin
// Initialize Inputs
D2_addr = 0;
IS62_WE = 1;
IS62_RD = 1;
D2CS_N = 1;
fpga_clk = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
repeat (50)
begin
#100;
D2CS_N=0;
#10;
IS62_WE=0;
D2_addr = ADDR1 ;
data_c= data_t;
#30;
IS62_WE=1;
data_c=1'bz;
D2_addr=1'bz;
#20;
D2CS_N=1;
#20;
ADDR1=ADDR1+1;
//ADDR2=ADDR2+1;
data_t=data_t+2;
end
#10000;
data_t=1'b1;
ADDR1=1'b0;
repeat (50)
begin
D2_addr = ADDR1;
#100;
D2CS_N=0;
#10;
IS62_RD=0;
#40;
IS62_RD=1;
DataR[ADDR2]=D2_dataout;
#20;
D2CS_N=1;
#20;
D2_addr=1'bz;
ADDR1=ADDR1+1;
ADDR2=ADDR2+1;
end
end
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