APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7946 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7946 with all its analog signals on the left side and all its
digital signals on the right side eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7946 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided
At least one ground plane should be used. It could be common
or split between the digital and analog section. In such a case, it
should be joined underneath the AD7946s.
The AD7946 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. That is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connect these pins with wide, low
impedance traces.
Finally, the power supply VDD and VIO of the AD7946 should
be decoupled with ceramic capacitors, typically 100 nF, placed
close to the AD7946 and connected using short and large traces
to provide low impedance paths and reduce the effect of glitches
on the power supply lines.
An example of layout following these rules is shown in Figure
41 and Figure 42.
EVALUATING THE AD7946’S PERFORMANCE
Other recommended layouts for the AD7946 are outlined in the
evaluation board for the AD7946 (EVAL-AD7946). The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling |
