68013做图像采集上位机收到的每一帧数据长度都不一样怎么回事,采用外部中断区分每一帧
- void TD_Init(void) // Called once at startup
- {
-
- // set the CPU clock to 48MHz
- CPUCS = 0x0a;//0x0a 0x12((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ; CPU clock frequency is 24MHz and CLKOUT 信号不被转换(as shown in all timing diagrams) and 驱动CLKOUT引脚
- REVCTL = 0x03 ;// 设置REVCTL. 0 和REVCTL. 1 为1 D1=1 不允许AUTOOUT从0到1翻转，D0=1允许CPU发数据包
- // REVCTL.1 ( DYN_OUT ) : 1 = disable autoarming on 0 to 1 transition of AUTOOUT
- // REVCTL.0 ( ENH_PKT ) : 1 = enable enhanched packet endling
- SYNCDELAY;
- FIFORESET = 0x80 ; // 复位EP2 FIFO
- SYNCDELAY;
- FIFORESET = 0x02 ;
- SYNCDELAY;
- FIFORESET = 0x04 ;
- SYNCDELAY;
- FIFORESET = 0x06 ;
- SYNCDELAY;
- FIFORESET = 0x08 ;
- SYNCDELAY;
- FIFORESET = 0x00 ;
- SYNCDELAY;
- SYNCDELAY;
- EP2CFG= 0xE8 ;
- SYNCDELAY;
- EP4CFG= 0x00 ;
- SYNCDELAY;
- EP6CFG= 0x00 ;
- SYNCDELAY;
- EP8CFG= 0x00 ;
- SYNCDELAY;
- EP2FIFOCFG= 0x09 ;
- SYNCDELAY;
- EP4FIFOCFG= 0x00 ;
- SYNCDELAY;
- EP6FIFOCFG= 0x00 ;
- SYNCDELAY;
- EP8FIFOCFG= 0x00 ;
- SYNCDELAY;
- FIFOPINPOLAR = 0x04 ;
- SYNCDELAY;
- PORTACFG|=0x01;
- SYNCDELAY;
- PORTECFG=0x00;
- SYNCDELAY;
- EP2AUTOINLENH = 0x02 ;
- SYNCDELAY;
- EP2AUTOINLENL = 0x00 ;
- SYNCDELAY;
- PINFLAGSAB = 0x00; // 定义FLAGA为可编程标志, pointed to by FIFOADR[1:0]
- SYNCDELAY; // FLAGB as full flag, as pointed to by FIFOADR[1:0]
- PINFLAGSCD = 0x00; // FLAGC as empty flag, as pointed to by FIFOADR[1:0]
- IFCONFIG = 0x43;
- }
- void int0_isr(void) interrupt INT0_VECT
- {
- IFCONFIG=0x43;
- EP2FIFOBUF[0]=0xFF;
- EP2FIFOBUF[1]=0xFF;
- EP2FIFOBUF[2]=0xFF;
- EP2FIFOBUF[3]=0xFF;
-
- EP2BCH=0X02;
- EP2BCL=0X00;
- }
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