// counter.v
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:34:13 03/16/07
// Design Name:
// Module Name: counter
// Project Name:
// Target Device:
// Tool versions:
// Signal Description:
// clk_125:系统时钟信号
// rst_n: 系统复位信号
// cl, 清零信号
// s, 开关信号。输入数据小于239个时为0，编码电路继续输入。为1时断开输入，在接下的16个时钟周期里使寄存器值依次输出
// en, 乘法器使能信号产生
// q 计数器输出，仿真时作为编码电力数据输入
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module counter(
clk_125,//system clock signal
rst_n, //system reset signal
cl, //output clear to zero signal
s, //switch signal.while the number of input data smaller than 239,it is low and continually input data to encoder circuit.while it is high,orderly output the result of the REG to data output port.
en, //multiplier enable signal
q //the output of counter and used as the input data while run simulation
);
input clk_125,rst_n;
output cl;
output s;
output en;
output [7:0] q;
reg cl;
reg s;
reg en;
reg [7:0] q;
always@(posedge clk_125 or negedge rst_n)
begin
if(!rst_n) begin //系统复位具备最高的优先级
q <= 8'b0;
s <= 0;
cl <= 0;
en <= 0;
end
else
q <= q+1;
if(q >= 1 && q < 239)begin
s <= 0;
cl <= 0;
en <= 1;
end
else if(q >= 239 && q < 255)begin
s <= 1;
cl <= 0;
en <= 0;
end
else if(q == 255)begin
cl <= 1;
s <= 0;
end
end
endmodule
报的错误是cl,s,en,q不和已经存在的FF或者Latch匹配 郁闷 |
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