library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FIR IS
GENERIC
(
WIDTH : integer := 8
);
PORT
(
CLK,RESET_N : IN STD_LOGIC;
X : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
H : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
Y : INOUT std_logic_vector(2*WIDTH-1 DOWNTO 0)
);
END FIR;
ARCHITECTURE a OF FIR IS
TYPE MEM IS ARRAY(0 TO 7) OF std_logic_vector(2*WIDTH-1 DOWNTO 0);
signal sys_reset : std_logic;
signal c : integer range 0 to 7 :=0;
signal result_sum : std_logic_vector(2*WIDTH-1 DOWNTO 0);
signal result: MEM;
BEGIN
sys_reset <= RESET_N;
result_sum<=Y;
--Y(6)<=result(6);
--Y(5)<=result(5);
--Y(4)<=result(4);
--Y(3)<=result(3);
--Y(2)<=result(1);
--Y(0)<=result(0);
PROCESS (CLK,sys_reset)
BEGIN
IF CLK 'event and CLK='1' THEN
IF sys_reset='0' THEN
Y<="ZZZZZZZZZZZZZZZZ";
--result_sum<="0000000000000000";
END IF;
END IF;
END PROCESS;
PROCESS (CLK)
BEGIN
IF CLK 'event and CLK='1' THEN
result(c)<=X*H;
c<=c+1;
result_sum<=result_sum+result(c);
IF c>=7 THEN
c<=0;
result_sum<="0000000000000000";
END IF;
END IF;
END PROCESS ;
END a;
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