用quartus7.1编译一个计数器,源代码:
library ieee;
use ieee.std_logic_1164.all;
entity jxu_count10 is
port(din: in std_logic;
rst: in std_logic;
yout: out std_logic_vector(3 downto 0));
end jxu_count10;
architecture if_cnt of jxu_count10 is
signal count: std_logic_vector(3 downto 0);
begin
process(din,rst)
begin
if(rst='1') then
count<="0000";
elsif(din'event and din='1') then
count<=(count+1);
end if;
end process;
yout<=count;
end if_cnt;
编译不通过,主要错误显示:
Error (10327): VHDL error at jxu_count10.vhd(18): can't determine definition of operator ""+"" -- found 0 possible definitions
也就是说quartus7.1不认识这句代码的"+"号,太奇怪了.
count<=(count+1); |
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