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用quartus7.1编译一个计数器,源代码:<br /><br />library ieee;<br />use ieee.std_logic_1164.all;<br /><br />entity jxu_count10 is<br /> port(din: in std_logic;<br /> rst: in std_logic;<br /> yout: out std_logic_vector(3 downto 0));<br />end jxu_count10;<br /><br />architecture if_cnt of jxu_count10 is<br />signal count: std_logic_vector(3 downto 0);<br /> begin<br /> process(din,rst)<br /> begin<br /> if(rst='1') then<br /> count<="0000";<br /> elsif(din'event and din='1') then<br /> count<=(count+1);<br /> end if;<br /> end process;<br /> yout<=count;<br />end if_cnt;<br /><br />编译不通过,主要错误显示:<br />Error (10327): VHDL error at jxu_count10.vhd(18): can't determine definition of operator ""+"" -- found 0 possible definitions<br /><br />也就是说quartus7.1不认识这句代码的"+"号,太奇怪了.<br />count<=(count+1); |
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