--2008-08-18:AM
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY EXP02 IS
PORT
(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
DERECTION : IN STD_LOGIC;
CS1 : IN STD_LOGIC;
CS2 : IN STD_LOGIC;
WR : IN STD_LOGIC;
DAT8 : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END EXP02;
ARCHITECTURE A OF EXP02 IS
SIGNAL CONT14: STD_LOGIC_VECTOR(13 DOWNTO 0);
BEGIN
CONT:Process (CLK,RESET,DERECTION) --可逆计数器
begin
if RESET='0' then
CONT14<=(others=>'0');
elsif clk'event and clk='1' then
if DERECTION='1' then
CONT14<=CONT14+1;
elsif DERECTION='0' then
CONT14<=CONT14-1;
end if;
end if;
end Process CONT ;
LD:Process (CS1,CS2,WR) --可逆计数器
begin
if WR'event and WR='0' then
if CS1='0' and CS2='1' then
DAT8<=CONT14(7 DOWNTO 0);
elsif CS1='1' and CS2='0' then
DAT8(5 DOWNTO 0)<=CONT14(13 DOWNTO 8);
--else
--DAT8<="ZZZZZZZZ";
end if;
end if;
end Process LD ;
END A
要是取消下面两行就通不过编译，郁闷啊！
--else
--DAT8<="ZZZZZZZZ";
谁能帮帮我啊，在线等待~~~~~~~~~ |
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