我是初学者，这是书上的一段VHDL的移位寄存器程序，有些地方不是很明白，麻烦大家解释下。
library ieee;
use ieee.std_logic_1164.all;
entity 74_sl_165 is
port ( clk,c0: in std_logic;
md: in std_logic_vector(2 downto 0);
d : in std_logic_vector(7 downto 0);
qb: out std_logic_vector(7 downto 0);
cn: out std_logic);
end entity;
architecture behav of 74_sl_165 is
signal reg: std_logic_vector(7 downto 0);
signal cy : std_logic;
begin
process( clk,md,c0)
begin
if clk'event and clk='1' then
case md is
when "001"=> reg(0)<=c0;
reg(7 downto 1) <=reg (6 downto 0); cy<=reg(7);
when "010"=>reg(0)<=reg(7);
reg(7 downto 1)<=reg (6 downto 0);
when "011"=>reg(7)<=reg(0);
reg(6 downto 0)<= reg(7 downto 1);
when "100"=>reg(7)<=c0;
reg(6 downto 0)<=reg(7 downto 1);cy<=reg(0);
when "101"=>reg(7 downto 0)<= d(7 downto 0);
when others=> reg<=reg; cy<=cy;
end case;
end if;
end process;
qb(7 downto 0)<=reg(7 downto 0); cn<=cy;
end behav;
几点不明白的地方：
1.MD, D,CN这三个端口作用，如果MD是移位控制字那怎么是3位的，不都是2位吗。
2.cy<=reg(7)和cy<=reg(0)这两句的作用是什么呀？
3.这是个什么样寄存器，感觉和4个D触发器组成的寄存器不太一样。
呵呵，我是新手，大家别见笑，谢谢。
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