|
我是初学者，这是书上的一段VHDL的移位寄存器程序，有些地方不是很明白，麻烦大家解释下。<br /><br />library ieee;<br />use ieee.std_logic_1164.all;<br />entity 74_sl_165 is <br />port ( clk,c0: in std_logic;<br /> md: in std_logic_vector(2 downto 0);<br /> d : in std_logic_vector(7 downto 0);<br /> qb: out std_logic_vector(7 downto 0);<br /> cn: out std_logic);<br />end entity;<br />architecture behav of 74_sl_165 is<br />signal reg: std_logic_vector(7 downto 0);<br />signal cy : std_logic;<br />begin<br />process( clk,md,c0)<br />begin<br />if clk'event and clk='1' then<br />case md is<br />when "001"=> reg(0)<=c0;<br /> reg(7 downto 1) <=reg (6 downto 0); cy<=reg(7);<br />when "010"=>reg(0)<=reg(7);<br />reg(7 downto 1)<=reg (6 downto 0);<br />when "011"=>reg(7)<=reg(0);<br />reg(6 downto 0)<= reg(7 downto 1);<br />when "100"=>reg(7)<=c0;<br />reg(6 downto 0)<=reg(7 downto 1);cy<=reg(0);<br />when "101"=>reg(7 downto 0)<= d(7 downto 0);<br />when others=> reg<=reg; cy<=cy;<br />end case;<br />end if;<br />end process;<br />qb(7 downto 0)<=reg(7 downto 0); cn<=cy;<br />end behav;<br />几点不明白的地方：<br /><br />1.MD, D,CN这三个端口作用，如果MD是移位控制字那怎么是3位的，不都是2位吗。<br /><br />2.cy<=reg(7)和cy<=reg(0)这两句的作用是什么呀？<br /><br />3.这是个什么样寄存器，感觉和4个D触发器组成的寄存器不太一样。<br /><br />呵呵，我是新手，大家别见笑，谢谢。<br /> |
|
楼主
