LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY encoder8_3_B IS
PORT(
COIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SI_5:IN STD_LOGIC;
EN,RESET:IN STD_LOGIC;
COIN_CODE:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END encoder8_3_B;
ARCHITECTURE behavior OF encoder8_3_B IS
SIGNAL ADDER:INTEGER RANGE 0 TO 1;
BEGIN
PROCESS(EN,RESET,COIN,SI_5)
BEGIN
IF EN='1' THEN
IF RESET='1' THEN COIN_CODE<=X"0";ADDER<=0;
ELSIF RISING_EDGE(SI_5) THEN ADDER<=ADDER+1;
IF(ADDER=0 AND SI_5='1') THEN COIN_CODE<=X"1";
END IF;
ELSE
CASE COIN IS
WHEN X"01"=> NULL;
WHEN X"02"=> COIN_CODE<=X"1";
WHEN X"04"=> COIN_CODE<=X"1";
WHEN X"08"=> COIN_CODE<=X"2";
WHEN X"10"=> COIN_CODE<=X"5";
WHEN X"20"=> COIN_CODE<=X"A";
WHEN OTHERS=> COIN_CODE<=X"0";
END CASE;
END IF;
ELSE COIN_CODE<=X"0";ADDER<=0;
END IF;
END PROCESS;
END behavior;
出错信息：
Error (10818): Can't infer register for "COIN_CODE[0]" at encoder8_3_B.vhd(17) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "COIN_CODE[1]" at encoder8_3_B.vhd(17) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "COIN_CODE[2]" at encoder8_3_B.vhd(17) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "COIN_CODE[3]" at encoder8_3_B.vhd(17) because it does not hold its value outside the clock edge
Error (10822): HDL error at encoder8_3_B.vhd(18): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 6 errors, 0 warnings
Info: Allocated 152 megabytes of memory during processing
Error: Processing ended: Mon Sep 08 16:56:26 2008
Error: Elapsed time: 00:00:03
Error: Quartus II Full Compilation was unsuccessful. 6 errors, 0 warnings
中间空出的两行为显示出错的地方，请高手赐教啊！ |
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