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veilog驱动液晶hd44780的问题

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txhong|  楼主 | 2008-11-23 10:05 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
这是我编写的驱动程序,我的仿真图像也符合器件本身的时序。不知道什么原因就是液晶没有显示的
module lcd1 (clk0,rst,lcd_data,rs,rw,en,cont);
   input clk0,rst;
   output [7:0] lcd_data;
   output rs,rw,en,cont;
   reg rs,rw,cont;
   reg [7:0] lcd_data;
   reg [3:0] state;
   reg [3:0] count;
  
parameter [3:0]
 warmup = 4'b0000,
 funcset= 4'b0001,
 dspoff = 4'b0011,
 clrdsp = 4'b0010,
 modeset= 4'b0110,
 dspon  = 4'b0111,
 setaddr= 4'b0101,
 write  = 4'b0100;
 initial
   begin
     //en=1;
     count=4'b0000;    
     state=warmup;
     cont=1;
     end 

always @ (posedge clk0 or negedge rst  )
 begin
   if(!rst) 
       begin
          count=4'b0000;    
          state=warmup;
       end
   else
       begin
            
            case(state)
                 warmup  : begin 
                             if(count==4'b0111)
                               begin
                               count=4'b0000;
                               state=funcset;
                               end
                             else begin
                                count=count+4'b0001;
                                state=warmup;
                                 end
                             end
                 funcset :  begin 
                             if(count==4'b1111)
                               begin
                               count=4'b0000;
                               state=dspoff;
                               end
                             else begin
                                count=count+4'b0001;
                                state=funcset;
                                 end
                             end
                 dspoff : state=clrdsp; 
                 clrdsp:  begin 
                             if(count==4'b0101)
                               begin
                               count=4'b0000;
                               state=modeset;
                               end
                             else begin
                                count=count+4'b0001;
                                state=clrdsp;
                                 end
                             end
                modeset:  state=dspon;
                 dspon: begin 
                             if(count==4'b0100)
                               begin
                               count=4'b0000;
                               state=setaddr;
                               end
                             else begin
                                count=count+4'b0001;
                                state=dspon;
                                 end
                             end
                setaddr: state=write;
                write : begin   
                           if(count==4'b0011)
                              begin
                                count=4'b0000;
                                state=warmup;
                              end
                           else begin
                                count=count+4'b0001;
                                state=write;
                                end
                        end                                                    
               default : state=warmup;
            endcase  
       end
 end

always @ (state or count )
       begin
         case(state)
             warmup : begin
                          rs=0;
                          rw=0; 
                          lcd_data=8'b00000000;
                      end
             funcset:lcd_data=8'b00111000;
             dspoff :lcd_data=8'b00001000;
             clrdsp :lcd_data=8'b00000001;
             modeset:lcd_data=8'b00000110;
               dspon:lcd_data=8'b00001100;
             setaddr: begin
                          rs=0;
                          rw=0; 
                          lcd_data=8'b10000000; 
                      end
              write  : begin
                          rs=1;
                          rw=0; 
                           case(count)
                                 'b0000 : lcd_data=8'b01000001; 
                                 'b0001 : lcd_data=8'b01000001; 
                                 'b0010 : lcd_data=8'b01000001; 
                                 'b0011 : lcd_data=8'b01000001; 
                                 default: lcd_data=8'b01000010; 
                           endcase
                       end
            default  :lcd_data=8'bzzzzzzzz;
          endcase                
       end
 assign en=clk0;
endmodule
     

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