今天郁闷了一天,麻烦大侠们帮我看一下.
想写一条程序实现单片机并行发数据3个8位的数据给FPGA,共24位,FPGA提取前20位.一个时钟口和一个FPGA数据输出使能.时钟由单片机控制,每个时钟周期输入8位数据.程序如下,可就是实现不了.能帮个忙说下哪里没弄好吗?
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
Use ieee.std_logic_unsigned.all;
Entity Buf is
port(datain:in std_logic_vector(7 downto 0);--数据进
clk :in std_logic;--时钟
en :in std_logic;--输出使能
dataout:inout std_logic_vector(19 downto 0)--数据出
);
end Buf;
architecture rtl of Buf is
signal databuf:std_logic_vector(23 downto 0);
signal count:std_logic_vector(1 downto 0);
begin
process(clk)
begin
if(clk 'event and clk='1')then
if(count="10")then
count<="00";
else count<=count+1;
end if;
end if;
end process;
process(count)
begin
CASE count IS
WHEN "00" =>
databuf(23 downto 16)<=datain;
WHEN "01" =>
databuf(15 downto 8)<=datain;
WHEN "10"=>
databuf(7 downto 0)<=datain;
WHEN others =>
databuf<=databuf;
END CASE;
end process;
process(clk)
begin
if(en='1')then
dataout<=databuf(19 downto 0);
else dataout<=dataout;
end if;
end process;
end rtl; |
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