小弟刚学VHDL不久，昨天写了一个状态机，在仿真的时候，发现状态的转换跟我预期的不
一样，是两个周期才转换一次。实在找不出问题，就慢慢的删程序，最后把程序删到了只
有状态转换部分，但是仿真出来还是两个周期才切换一次状态。
我感觉应该是一个周期转换一次状态才对。
不知道是我的理解有问题，还是程序有问题。
我把代码贴在下面了，麻烦各位帮我看看。
谢谢了！！！
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NonStopWrite is
port(
clk:in std_logic;
rst:in std_logic
) ;
end NonStopWrite;
architecture Behavioral of NonStopWrite is
type NonStopState is (IDLE,WR1,WR2,WR3,WR4,WR5);
signal pre_state,next_state: NonStopState;
begin
process(clk,rst)
begin
if(rst='1')then
next_state <= IDLE;
elsif(rising_edge(clk))then
case pre_state is
when IDLE =>
next_state <= WR1;
when WR1 =>
next_state <= WR2;
when WR2 =>
next_state <= WR3;
when WR3 =>
next_state <= WR4;
when WR4 =>
next_state <= WR5;
when WR5 =>
next_state <= WR1;
when others=>
next_state <= IDLE;
end case;
end if;
end process;
process(clk,rst)
begin
if(rst='1')then
pre_state <= IDLE;
elsif(rising_edge(clk))then
pre_state <= next_state;
end if;
end process;
end Behavioral;
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