VHDL程序求救
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;
entity frqctl is
port(frq_chg:in std_logic_vector(3 downto 0);
q_out:out integer range 0 to 100000);--std_logic_vector(15 downto 0));
end frqctl;
architecture a of frqctl is
begin
--temp<=10000;--"0010011100010000";
process (frq_chg)
variable temp:integer range 1000 to 20000;--std_logic_vector(15 downto 0);
--variable b:integer ;
begin
temp:=10000;
if frq_chg(0)='0' then
temp:=temp+1;
elsif frq_chg(1)='0' then
temp:=temp-1;
elsif frq_chg(2)='0' then
temp:=temp+100;
elsif frq_chg(3)='0' then
temp:=temp-100;
end if;
--b:=1/temp;
q_out<=100000000/temp;
end process;
end a;
编译时总是出现right operand of "divide"operator must be a power of 2
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