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library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.std_logic_unsigned.all;<br />use ieee.std_logic_arith.all;<br /><br />entity chufa2 is<br />port(a:in std_logic_vector(0 to 31);--被除数<br /> b:in std_logic_vector(0 to 31);--除数<br /> c:inout std_logic_vector(0 to 31));--商<br />end chufa2;<br /><br />architecture abc of chufa2 is<br />signal c1:std_logic_vector(0 to 31);<br />begin<br /> process(a,b)<br /> variable b1:std_logic_vector(0 to 32);<br /> begin<br /> if b="00000000000000000000000000000000" then --b为全0<br /> c<=(others=>'1');<br /> elsif a<b then c<=(others=>'0');<br /> else <br /> c(1 to 31)<=(others=>'0');<br /> c(0)<='1';<br /> b1:='0'&b;<br /> l1: loop<br /> b1(1 to 32):=b1(0 to 31);--除数左移<br /> b1(0):='0';<br /> c(1 to 31)<=b1(0 to 30);--商*2<br /> c(0)<='0';<br /> exit l1 when a<b1;<br /> --end if;<br /> end loop l1;<br /> end if;<br /> end process;<br />end abc;<br />求救：为什么每次用quartus编译都出现 <br />Error (10536): VHDL Loop Statement error at chufa2.vhd(20): loop must terminate at or before 10000 iterations |
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