library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity chufa2 is
port(a:in std_logic_vector(0 to 31);--被除数
b:in std_logic_vector(0 to 31);--除数
c:inout std_logic_vector(0 to 31));--商
end chufa2;
architecture abc of chufa2 is
signal c1:std_logic_vector(0 to 31);
begin
process(a,b)
variable b1:std_logic_vector(0 to 32);
begin
if b="00000000000000000000000000000000" then --b为全0
c<=(others=>'1');
elsif a<b then c<=(others=>'0');
else
c(1 to 31)<=(others=>'0');
c(0)<='1';
b1:='0'&b;
l1: loop
b1(1 to 32):=b1(0 to 31);--除数左移
b1(0):='0';
c(1 to 31)<=b1(0 to 30);--商*2
c(0)<='0';
exit l1 when a<b1;
--end if;
end loop l1;
end if;
end process;
end abc;
求救：为什么每次用quartus编译都出现
Error (10536): VHDL Loop Statement error at chufa2.vhd(20): loop must terminate at or before 10000 iterations |
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