21ic电子技术开发论坛 › 综合技术交流 › EDA 技术 › 如何处理编译错误信息?
返回列表 发新帖我要提问

如何处理编译错误信息?

[复制链接]
4832|6
 楼主| qzx0580 发表于 2007-1-25 09:02 | 显示全部楼层 |阅读模式
编译, ni, pi, sam, warning
请教,我用VerilogHDL写了个小的程序,没有几行,但是错误不少.现将程序与错误信息贴出来请高人指点.谢先!<br />/******************************************************************************<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;VerilogHDL语言部分<br />******************************************************************************/<br />module&nbsp;Bus_Expand(TRIG,SELECT,SAMPIN,SAMPOUT,DATA);<br />input&nbsp;TRIG;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;//Signal&nbsp;that&nbsp;comes&nbsp;as&nbsp;trig&nbsp;from&nbsp;DSP<br />input&nbsp;SELECT;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;//Select&nbsp;the&nbsp;data&nbsp;direction,1=SAMPIN&nbsp;0=SAMPOUT&nbsp;<br />input&nbsp;[15:0]&nbsp;SAMPIN;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;//Declaration&nbsp;of&nbsp;the&nbsp;Sample&nbsp;in&nbsp;signal,16&nbsp;Channel<br />output&nbsp;[15:0]&nbsp;SAMPOUT;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;//Declaration&nbsp;of&nbsp;the&nbsp;Sample&nbsp;out&nbsp;signal,16&nbsp;Channel<br />inout&nbsp;[15:0]&nbsp;DATA;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;//Channels&nbsp;for&nbsp;data&nbsp;exchange&nbsp;between&nbsp;DSP&CPLD<br />reg&nbsp;[15:0]&nbsp;DATA;<br />reg&nbsp;[15:0]&nbsp;SAMPOUT;<br />reg&nbsp;[15:0]&nbsp;TEMP;<br />always&nbsp;@(TRIG&nbsp;or&nbsp;SELECT)<br />&nbsp;&nbsp;case({TRIG,&nbsp;SELECT})<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;10:begin&nbsp;TEMP&nbsp;&lt=SAMPIN;DATA&nbsp;&lt=TEMP;end&nbsp;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;11:begin&nbsp;TEMP&nbsp;&lt=DATA;SAMPOUT&nbsp;&lt=TEMP;end<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;default:begin&nbsp;DATA&nbsp;&lt=16'bz;SAMPOUT&nbsp;&lt=16'bz;TEMP&nbsp;&lt=16'bz;end<br />&nbsp;&nbsp;endcase<br />endmodule<br /><br />/******************************************************************************<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;管脚分配部分<br />******************************************************************************/在&nbsp;Assignment&nbsp;Editor中，我按照硬件电路图将相应输入输出管脚分配给了DATA,SAMPIN,SAMPOUT,TRIG,SELECT等管脚，但是我不知道怎么将全局时钟,还有JTAG管脚分配给CPLD，因为在module中不需用到这些管脚,在编译时出现如下的错误信息：<br /><br />/******************************************************************************<br />编译错误信息<br />******************************************************************************/<br />Warning&nbsp;(10199):&nbsp;Verilog&nbsp;HDL&nbsp;Case&nbsp;Statement&nbsp;warning&nbsp;at&nbsp;Bus_Expand.v(13):&nbsp;case&nbsp;item&nbsp;expression&nbsp;is&nbsp;ignored&nbsp;because&nbsp;it&nbsp;never&nbsp;applies<br /><br />Warning&nbsp;(10199):&nbsp;Verilog&nbsp;HDL&nbsp;Case&nbsp;Statement&nbsp;warning&nbsp;at&nbsp;Bus_Expand.v(14):&nbsp;case&nbsp;item&nbsp;expression&nbsp;is&nbsp;ignored&nbsp;because&nbsp;it&nbsp;never&nbsp;applies<br /><br />Warning:&nbsp;Design&nbsp;contains&nbsp;18&nbsp;input&nbsp;pin(s)&nbsp;that&nbsp;do&nbsp;not&nbsp;drive&nbsp;logic<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;TRIG&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SELECT&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[0]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[1]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[2]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[3]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[4]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[5]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[6]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[7]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[8]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[9]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[10]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[11]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[12]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[13]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[14]&quot;<br />&nbsp;&nbsp;&nbsp;&nbsp;Warning:&nbsp;No&nbsp;output&nbsp;dependent&nbsp;on&nbsp;input&nbsp;pin&nbsp;&quot;SAMPIN[15]&quot;<br />
回复

收藏 举报

相关帖子
 楼主| qzx0580 发表于 2007-1-25 14:16 | 显示全部楼层

请帮忙

请帮忙,谢谢.
回复

收藏 举报

 楼主| qzx0580 发表于 2007-1-25 15:41 | 显示全部楼层

没有回应?

没有回应?!
回复

收藏 举报

n3207 发表于 2007-1-25 20:51 | 显示全部楼层

试着想想你的代码实现的电路是什么？

好好想想你的代码实现的电路是什么。<br /><br />第二条告警是说那些信号没有驱动任何信号。<br /><br />第一条是说<br />CAUSE:&nbsp;In&nbsp;a&nbsp;Case&nbsp;Statement&nbsp;at&nbsp;the&nbsp;specified&nbsp;location&nbsp;in&nbsp;a&nbsp;Verilog&nbsp;Design&nbsp;File&nbsp;(.v),&nbsp;you&nbsp;specified&nbsp;a&nbsp;case&nbsp;item&nbsp;expression&nbsp;that&nbsp;has&nbsp;more&nbsp;significant&nbsp;bits&nbsp;than&nbsp;the&nbsp;number&nbsp;of&nbsp;bits&nbsp;in&nbsp;the&nbsp;case&nbsp;expression&nbsp;that&nbsp;it&nbsp;is&nbsp;being&nbsp;compared&nbsp;against.&nbsp;As&nbsp;a&nbsp;result,&nbsp;the&nbsp;case&nbsp;item&nbsp;expression&nbsp;can&nbsp;never&nbsp;apply,&nbsp;and&nbsp;is&nbsp;ignored&nbsp;by&nbsp;the&nbsp;Quartus&nbsp;II&nbsp;software.&nbsp;<br />ACTION:&nbsp;No&nbsp;action&nbsp;is&nbsp;required.&nbsp;To&nbsp;avoid&nbsp;receiving&nbsp;this&nbsp;message&nbsp;in&nbsp;the&nbsp;future,&nbsp;remove&nbsp;bits&nbsp;from&nbsp;the&nbsp;case&nbsp;item&nbsp;expression&nbsp;until&nbsp;the&nbsp;bit&nbsp;length&nbsp;matches&nbsp;that&nbsp;of&nbsp;the&nbsp;case&nbsp;expression.&nbsp;<br /><br />最后要说，要好好看看阻塞与非阻塞的区别。
回复

收藏 举报

 楼主| qzx0580 发表于 2007-1-26 14:09 | 显示全部楼层

电路功能

这个电路要实现的功能就是总线扩展,基本上不涉及到时序,只是逻辑上的组合.<br />这些错误提示我向专人请教过,发现是always以下的语句都不执行.问题可能出在条件不满足,我思考了一下,觉得可能是always&nbsp;@()这样的语句应该用在时序逻辑电路中,而不适合组合逻辑,现在改成了always&nbsp;@&nbsp;(posedge&nbsp;CLK)再编译就只出现一个CLK没有配置的警告了,我想大概是我不会配置CLK管脚造成的.楼上的朋友能指点一下如何配置时钟管脚以及暂时闲置的管脚吗?<br /><br />非常感谢.<br /><br />我反复看过阻塞赋值与非阻塞赋值语句,觉得两都就是在时序上有所不同,一个类似于串行赋值,另一个类似于并行赋值.不知道这样的理解有没有错?
回复

收藏 举报

 楼主| qzx0580 发表于 2007-1-26 15:56 | 显示全部楼层

说错了.

关于always&nbsp;的说法是错误的,因为在教程上看到了类似的语句,我想不是always&nbsp;@(TRIG&nbsp;or&nbsp;SELECT)这个句子的错,敬请有经验的朋友指点.
回复

收藏 举报

n3207 发表于 2007-2-1 20:33 | 显示全部楼层

你可以使用综合工具或者quartusii编译一下

编译后就看看电路是不是你想要的电路就清楚了。
回复

收藏 举报

返回列表 发新帖
高级模式
B Color Image Link Quote Code Smilies
您需要登录后才可以回帖 登录 | 注册

本版积分规则

qzx0580

28

主题

172

帖子

0

粉丝
快速回复 在线客服 返回列表 返回顶部