终于在5410的DATASHEET中 INTERRUPT TIMING部分找到
The external interrupts (INT0−INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1−0−0 sequence at the timing that is
corresponding to three CLKOUTs sampling sequence.
另外在TI网站上找到一个类似的问题及解答
http://www-k.ext.ti.com/srvs/cgi-bin/webcgi.exe?Company={5761bcd8-11f5-4e08-84e0-8167176a4ed9},kb=dsp,case=31784,new
Are the C55x DSP interrupt pins level- or edge-triggered?
Problem:
Are the C55x DSP interrupt pins level- or edge-triggered?
Solution:
It can be considered as edge triggered (falling edge) but with an additional low pulse width requirement. A sequence on the interrupt pin of a logic one followed by several 0s on consecutive cycles is required for an interrupt to be detected. See the External Interrupt Timings section of the data manual for details.
结论：C54与C55外部中断触发方式基本一样 ，类似边沿触发，CLOUT下降沿采样，但是对PIN的电平有要求。。
如5410需要1-0-0
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