The external interrupts (INT0−INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1−0−0 sequence at the timing that is
corresponding to three CLKOUTs sampling sequence.
Are the C55x DSP interrupt pins level- or edge-triggered?
Problem:
Are the C55x DSP interrupt pins level- or edge-triggered?
Solution:
It can be considered as edge triggered (falling edge) but with an additional low pulse width requirement. A sequence on the interrupt pin of a logic one followed by several 0s on consecutive cycles is required for an interrupt to be detected. See the External Interrupt Timings section of the data manual for details.
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