这是一个 带清零的8位并行加载移位寄存器；
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ks is
port (clk:in std_logic;
a,b,c,d,e,f,g,h:in std_logic;
fe,sl,clr:in std_logic;
q:out std_logic);
end;
architecture one of ks is
signal temp:std_logic_vector(7 downto 0);
begin
process(clk,sl,fe,clr)
begin
if (clr='0')then
temp<="00000000";
q<=temp(7);
elsif((clk'event) and (clk='1')and fe='0')then
if (sl='0')then
temp(0)<=a;
temp(1)<=temp(0);
temp(2)<=temp(1);
temp(3)<=temp(2);
temp(4)<=temp(3);
temp(5)<=temp(4);
temp(6)<=temp(5);
temp(7)<=temp(6);
q<=temp(7);
end if;
end if;
end process;
end; |
楼主
标题置顶
标题高亮
