/* Private define ------------------------------------------------------------*/
#define WRITE 0x82 /* Write to Memory instruction */
#define READ 0xD3 /* Read from Memory instruction */
#define RDSR 0xD7 /* Read Status Register instruction */
#define RDID 0x9F /* Read identification */
#define PE 0x81 /* Page Erase instruction */
#define BE1 0xC7 /* Bulk Erase instruction */
#define BE2 0x94 /* Bulk Erase instruction */
#define BE3 0x80 /* Bulk Erase instruction */
#define BE4 0x9A /* Bulk Erase instruction */
#define BUSY_Flag 0x01 /* Ready/busy status flag */
#define Dummy_Byte 0xff
/*******************************************************************************/
#define WRITE_BURST 0x40 //连续写入
#define READ_SINGLE 0x80 //读
#define READ_BURST 0xC0 //连续读
#define BYTES_IN_RXFIFO 0x7F //接收缓冲区的有效字节数
#define CRC_OK 0x80 //CRC校验通过位标志
// CC1100 STROBE, CONTROL AND STATUS REGSITER
#define CCxxx0_IOCFG2 0x00 // GDO2 output pin configuration
#define CCxxx0_IOCFG1 0x01 // GDO1 output pin configuration
#define CCxxx0_IOCFG0 0x02 // GDO0 output pin configuration
#define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
#define CCxxx0_SYNC1 0x04 // Sync word, high uint8_t
#define CCxxx0_SYNC0 0x05 // Sync word, low uint8_t
#define CCxxx0_PKTLEN 0x06 // Packet length
#define CCxxx0_PKTCTRL1 0x07 // Packet automation control
#define CCxxx0_PKTCTRL0 0x08 // Packet automation control
#define CCxxx0_ADDR 0x09 // Device address
#define CCxxx0_CHANNR 0x0A // Channel number
#define CCxxx0_FSCTRL1 0x0B // Frequency synthesizer control
#define CCxxx0_FSCTRL0 0x0C // Frequency synthesizer control
#define CCxxx0_FREQ2 0x0D // Frequency control word, high uint8_t
#define CCxxx0_FREQ1 0x0E // Frequency control word, middle uint8_t
#define CCxxx0_FREQ0 0x0F // Frequency control word, low uint8_t
#define CCxxx0_MDMCFG4 0x10 // Modem configuration
#define CCxxx0_MDMCFG3 0x11 // Modem configuration
#define CCxxx0_MDMCFG2 0x12 // Modem configuration
#define CCxxx0_MDMCFG1 0x13 // Modem configuration
#define CCxxx0_MDMCFG0 0x14 // Modem configuration
#define CCxxx0_DEVIATN 0x15 // Modem deviation setting
#define CCxxx0_MCSM2 0x16 // Main Radio Control State Machine configuration
#define CCxxx0_MCSM1 0x17 // Main Radio Control State Machine configuration
#define CCxxx0_MCSM0 0x18 // Main Radio Control State Machine configuration
#define CCxxx0_FOCCFG 0x19 // Frequency Offset Compensation configuration
#define CCxxx0_BSCFG 0x1A // Bit Synchronization configuration
#define CCxxx0_AGCCTRL2 0x1B // AGC control
#define CCxxx0_AGCCTRL1 0x1C // AGC control
#define CCxxx0_AGCCTRL0 0x1D // AGC control
#define CCxxx0_WOREVT1 0x1E // High uint8_t Event 0 timeout
#define CCxxx0_WOREVT0 0x1F // Low uint8_t Event 0 timeout
#define CCxxx0_WORCTRL 0x20 // Wake On Radio control
#define CCxxx0_FREND1 0x21 // Front end RX configuration
#define CCxxx0_FREND0 0x22 // Front end TX configuration
#define CCxxx0_FSCAL3 0x23 // Frequency synthesizer calibration
#define CCxxx0_FSCAL2 0x24 // Frequency synthesizer calibration
#define CCxxx0_FSCAL1 0x25 // Frequency synthesizer calibration
#define CCxxx0_FSCAL0 0x26 // Frequency synthesizer calibration
#define CCxxx0_RCCTRL1 0x27 // RC oscillator configuration
#define CCxxx0_RCCTRL0 0x28 // RC oscillator configuration
#define CCxxx0_FSTEST 0x29 // Frequency synthesizer calibration control
#define CCxxx0_PTEST 0x2A // Production test
#define CCxxx0_AGCTEST 0x2B // AGC test
#define CCxxx0_TEST2 0x2C // Various test settings
#define CCxxx0_TEST1 0x2D // Various test settings
#define CCxxx0_TEST0 0x2E // Various test settings
// Strobe commands
#define CCxxx0_SRES 0x30 // Reset chip.
#define CCxxx0_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
// If in RX/TX: Go to a wait state where only the synthesizer is
// running (for quick RX / TX turnaround).
#define CCxxx0_SXOFF 0x32 // Turn off crystal oscillator.
#define CCxxx0_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
// (enables quick start).
#define CCxxx0_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
// MCSM0.FS_AUTOCAL=1.
#define CCxxx0_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
// MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled:
// Only go to TX if channel is clear.
#define CCxxx0_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
// Wake-On-Radio mode if applicable.
#define CCxxx0_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
#define CCxxx0_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
#define CCxxx0_SPWD 0x39 // Enter power down mode when CSn goes high.
#define CCxxx0_SFRX 0x3A // Flush the RX FIFO buffer.
#define CCxxx0_SFTX 0x3B // Flush the TX FIFO buffer.
#define CCxxx0_SWORRST 0x3C // Reset real time clock.
#define CCxxx0_SNOP 0x3D // No operation. May be used to pad strobe commands to two
// uint8_ts for simpler software.
#define CCxxx0_PARTNUM 0x30
#define CCxxx0_VERSION 0x31
#define CCxxx0_FREQEST 0x32
#define CCxxx0_LQI 0x33
#define CCxxx0_RSSI 0x34
#define CCxxx0_MARCSTATE 0x35
#define CCxxx0_WORTIME1 0x36
#define CCxxx0_WORTIME0 0x37
#define CCxxx0_PKTSTATUS 0x38
#define CCxxx0_VCO_VC_DAC 0x39
#define CCxxx0_TXBYTES 0x3A
#define CCxxx0_RXBYTES 0x3B
#define CCxxx0_PATABLE 0x3E
#define CCxxx0_TXFIFO 0x3F
#define CCxxx0_RXFIFO 0x3F
typedef struct S_RF_SETTINGS
{
uint8_t FSCTRL2; //自已加的
uint8_t FSCTRL1; // Frequency synthesizer control.
uint8_t FSCTRL0; // Frequency synthesizer control.
uint8_t FREQ2; // Frequency control word, high uint8_t.
uint8_t FREQ1; // Frequency control word, middle uint8_t.
uint8_t FREQ0; // Frequency control word, low uint8_t.
uint8_t MDMCFG4; // Modem configuration.
uint8_t MDMCFG3; // Modem configuration.
uint8_t MDMCFG2; // Modem configuration.
uint8_t MDMCFG1; // Modem configuration.
uint8_t MDMCFG0; // Modem configuration.
uint8_t CHANNR; // Channel number.
uint8_t DEVIATN; // Modem deviation setting (when FSK modulation is enabled).
uint8_t FREND1; // Front end RX configuration.
uint8_t FREND0; // Front end RX configuration.
uint8_t MCSM0; // Main Radio Control State Machine configuration.
uint8_t FOCCFG; // Frequency Offset Compensation Configuration.
uint8_t BSCFG; // Bit synchronization Configuration.
uint8_t AGCCTRL2; // AGC control.
uint8_t AGCCTRL1; // AGC control.
uint8_t AGCCTRL0; // AGC control.
uint8_t FSCAL3; // Frequency synthesizer calibration.
uint8_t FSCAL2; // Frequency synthesizer calibration.
uint8_t FSCAL1; // Frequency synthesizer calibration.
uint8_t FSCAL0; // Frequency synthesizer calibration.
uint8_t FSTEST; // Frequency synthesizer calibration control
uint8_t TEST2; // Various test settings.
uint8_t TEST1; // Various test settings.
uint8_t TEST0; // Various test settings.
uint8_t IOCFG2; // GDO2 output pin configuration
uint8_t IOCFG0; // GDO0 output pin configuration
uint8_t PKTCTRL1; // Packet automation control.
uint8_t PKTCTRL0; // Packet automation control.
uint8_t ADDR; // Device address.
uint8_t PKTLEN; // Packet length.
} RF_SETTINGS;
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 0.000000
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 433.000000 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2) 4 bytes
// Append status = 1
// Address check = (11) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6)
// GDO2 signal selection = (11) Serial Clock
const RF_SETTINGS rfSettings = {
0x00,
0x06, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x10, // FREQ2 Frequency control word, high byte.
0xb1, // FREQ1 Frequency control word, middle byte.
0x3b, // FREQ0 Frequency control word, low byte.
0xf6, // MDMCFG4 Modem configuration.
0x83, // MDMCFG3 Modem configuration.
0x13, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xf8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x15, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0x56, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end RX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x16, // FOCCFG Frequency Offset Compensation Configuration.
0x6c, // BSCFG Bit synchronization Configuration.
0x03, // AGCCTRL2 AGC control.
0x40, // AGCCTRL1 AGC control.
0x91, // AGCCTRL0 AGC control.
0xe9, // FSCAL3 Frequency synthesizer calibration.
0x2a, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x1f, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x81, // TEST2 Various test settings.
0x35, // TEST1 Various test settings.
0x09, // TEST0 Various test settings.
0x29, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
0x04, // PKTCTRL1 Packet automation control.
0x05, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
0x0c // PKTLEN Packet length.
};
void halRfWriteRfSettings(void)
{
Read_Reg_Value=halSpiReadReg(CCxxx0_FSCTRL1);
halSpiWriteReg(CCxxx0_FSCTRL0, rfSettings.FSCTRL2);//自已加的
// Write register settings
halSpiWriteReg(CCxxx0_FSCTRL1, rfSettings.FSCTRL1);
halSpiWriteReg(CCxxx0_FSCTRL0, rfSettings.FSCTRL0);
halSpiWriteReg(CCxxx0_FREQ2, rfSettings.FREQ2);
halSpiWriteReg(CCxxx0_FREQ1, rfSettings.FREQ1);
halSpiWriteReg(CCxxx0_FREQ0, rfSettings.FREQ0);
halSpiWriteReg(CCxxx0_MDMCFG4, rfSettings.MDMCFG4);
halSpiWriteReg(CCxxx0_MDMCFG3, rfSettings.MDMCFG3);
halSpiWriteReg(CCxxx0_MDMCFG2, rfSettings.MDMCFG2);
halSpiWriteReg(CCxxx0_MDMCFG1, rfSettings.MDMCFG1);
halSpiWriteReg(CCxxx0_MDMCFG0, rfSettings.MDMCFG0);
halSpiWriteReg(CCxxx0_CHANNR, rfSettings.CHANNR);
halSpiWriteReg(CCxxx0_DEVIATN, rfSettings.DEVIATN);
halSpiWriteReg(CCxxx0_FREND1, rfSettings.FREND1);
halSpiWriteReg(CCxxx0_FREND0, rfSettings.FREND0);
halSpiWriteReg(CCxxx0_MCSM0, rfSettings.MCSM0);
halSpiWriteReg(CCxxx0_FOCCFG, rfSettings.FOCCFG);
halSpiWriteReg(CCxxx0_BSCFG, rfSettings.BSCFG);
halSpiWriteReg(CCxxx0_AGCCTRL2, rfSettings.AGCCTRL2);
halSpiWriteReg(CCxxx0_AGCCTRL1, rfSettings.AGCCTRL1); //
halSpiWriteReg(CCxxx0_AGCCTRL0, rfSettings.AGCCTRL0);
halSpiWriteReg(CCxxx0_FSCAL3, rfSettings.FSCAL3);
halSpiWriteReg(CCxxx0_FSCAL2, rfSettings.FSCAL2);
halSpiWriteReg(CCxxx0_FSCAL1, rfSettings.FSCAL1); ///
halSpiWriteReg(CCxxx0_FSCAL0, rfSettings.FSCAL0);
halSpiWriteReg(CCxxx0_FSTEST, rfSettings.FSTEST);
halSpiWriteReg(CCxxx0_TEST2, rfSettings.TEST2);
halSpiWriteReg(CCxxx0_TEST1, rfSettings.TEST1);
halSpiWriteReg(CCxxx0_TEST0, rfSettings.TEST0);
halSpiWriteReg(CCxxx0_IOCFG2, rfSettings.IOCFG2);
halSpiWriteReg(CCxxx0_IOCFG0, rfSettings.IOCFG0);
halSpiWriteReg(CCxxx0_PKTCTRL1, rfSettings.PKTCTRL1);
halSpiWriteReg(CCxxx0_PKTCTRL0, rfSettings.PKTCTRL0);
halSpiWriteReg(CCxxx0_ADDR, rfSettings.ADDR);
halSpiWriteReg(CCxxx0_PKTLEN, rfSettings.PKTLEN);
halSpiWriteBurstReg(CCxxx0_PATABLE, PaTabel, 8);
//for test
}
//发送过程 ，每100ms发送一次
halRfSendPacket(buf,8); //写buffer
void halRfSendPacket(uint8_t *txBuffer, uint8_t size)
{
halSpiWriteReg(CCxxx0_TXFIFO, size);
halSpiWriteBurstReg(CCxxx0_TXFIFO, txBuffer, size); //写入要发送的数据
halSpiStrobe(CCxxx0_SIDLE);
halSpiStrobe(CCxxx0_STX); //进入发送模式发送数据
// Wait for GDO0 to be set -> sync transmitted
//while (!GPIO_ReadInputDataBit(GPIOA,GPIO_Pin_GD0));//while (!GDO0);
// Wait for GDO0 to be cleared -> end of packet
//while (GPIO_ReadInputDataBit(GPIOA,GPIO_Pin_GD0));// while (GDO0);
//halSpiStrobe(CCxxx0_SFTX);
} |
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