各位好！
以下程序：不分接收模块，在FPGA030板子上实验OK；但分了模块后就不能正常！
请大家帮忙分析：
module com( clk,
rst,
rxd,
Data_out
);
input clk;
input rst;
input rxd;
output [7:0] Data_out;
reg [7:0] Data_out;
wire [7:0] LED1;
wire bclk;
//波特率?
bclk_gen bclk0(
.clk(clk),
.bclk(bclk)
);
//接收模块
uart_rx uart_rx0(
.bclk(bclk),
.rxd(rxd),
.LED1(LED1)
// .Data_out(Data_out),
//.uart_tx_buff(uart_tx_buff)
);
always @(posedge clk)
begin
if(!rst)
begin
Data_out = 8'b00000000;
end
else if(bclk)
begin
case(LED1) //用于开发板上的4位LED编码显示
8'd0 : Data_out=8'b00000000;
8'd1 : Data_out=8'b00000001;
8'd2 : Data_out=8'b00000010;
8'd3 : Data_out=8'b00000011;
8'd4 : Data_out=8'b00000100;
8'd5 : Data_out=8'b00000101;
8'd6 : Data_out=8'b00000110;
8'd7 : Data_out=8'b00000111;
8'd8 : Data_out=8'b00001000;
8'd9 : Data_out=8'b00001001;
8'd10 : Data_out=8'b00001010;
8'd11 : Data_out=8'b00001011;
8'd12 : Data_out=8'b00001100;
8'd13 : Data_out=8'b00001101;
8'd14 : Data_out=8'b00001110;
8'd15 : Data_out=8'b00001111;
default : Data_out=8'b11111111;
endcase
end
else Data_out = 8'b00000000;
end
endmodule
module bclk_gen (
clk,
bclk
);
input clk;
output bclk;
reg bclk;
reg [15:0] cnt1; // 时钟节拍计数器
parameter cout=312; // 分频数
always @(posedge clk)
begin
if(cnt1==cout)
begin
bclk<=1;
cnt1<=16'd0;
end
else
begin
cnt1<=cnt1+1'b1;
bclk<=0;
end
end
endmodule
// uart_rx.v
module uart_rx(
bclk,
rxd,
LED1
);
input bclk;
input rxd;
output [7:0] LED1;
reg [7:0] LED;
parameter [3:0] Lframe_rx = 8;
parameter [2:0] s_idle_rx= 3'b000;
parameter [2:0] s_sample_rx = 3'b001;
parameter [2:0] s_stop_rx = 3'b010;
reg [2:0] state_rx = s_idle_rx;
reg [3:0] cnt_rx = 0;
reg [3:0] num_rx = 0;
reg [3:0] dcnt_rx = 0;
assign LED1 = LED;
always @(posedge bclk)
begin
case(state_rx)
s_idle_rx:
begin
LED <=0;
dcnt_rx <=0;
if(cnt_rx == 4'b1111)
begin
cnt_rx <=0;
if(num_rx>7)
begin
state_rx <=s_sample_rx;
num_rx <=0;
end
else
begin
state_rx <=s_idle_rx;
num_rx <=0;
end
end
else
begin
cnt_rx <= cnt_rx+1;
if(rxd == 1'b0)
begin
num_rx <=num_rx +1;
end
else
begin
num_rx <=num_rx;
end
end
end
s_sample_rx:
begin
if(dcnt_rx == Lframe_rx)
begin
state_rx <= s_stop_rx;
end
else
begin
state_rx <= s_sample_rx;
if(cnt_rx == 4'b1111)
begin
dcnt_rx <=dcnt_rx +1;
cnt_rx <=0;
if(num_rx >7)
begin
num_rx <=0;
LED[dcnt_rx] <=1;
end
else
begin
LED[dcnt_rx] <=0;
num_rx <=0;
end
end
else
begin
cnt_rx <=cnt_rx+1;
if(rxd == 1'b1)
begin
num_rx <=num_rx+1;
end
else
begin
num_rx<=num_rx;
end
end
end
end
s_stop_rx:
begin
if(cnt_rx ==4'b1111)
begin
cnt_rx <=0;
state_rx <=s_idle_rx;
end
else
begin
cnt_rx <=cnt_rx +1;
end
end
endcase
end
endmodule |
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