typedef struct {
__IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
__O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
__O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} GPIO_Type, *GPIO_MemMapPtr;
/* GPIO - Peripheral instance base addresses */
/** Peripheral PTA base address */
#define PTA_BASE (0x400FF000u)
/** Peripheral PTA base pointer */
#define PTA ((GPIO_Type *)PTA_BASE)
#define PTA_BASE_PTR (PTA)
/** Peripheral PTB base address */
#define PTB_BASE (0x400FF040u)
/** Peripheral PTB base pointer */
#define PTB ((GPIO_Type *)PTB_BASE)
#define PTB_BASE_PTR (PTB)
/** Peripheral PTC base address */
#define PTC_BASE (0x400FF080u)
/** Peripheral PTC base pointer */
#define PTC ((GPIO_Type *)PTC_BASE)
#define PTC_BASE_PTR (PTC)
/** Peripheral PTD base address */
#define PTD_BASE (0x400FF0C0u)
/** Peripheral PTD base pointer */
#define PTD ((GPIO_Type *)PTD_BASE)
#define PTD_BASE_PTR (PTD)
/** Peripheral PTE base address */
#define PTE_BASE (0x400FF100u)
/** Peripheral PTE base pointer */
#define PTE ((GPIO_Type *)PTE_BASE)
#define PTE_BASE_PTR (PTE)
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
#define GPIO_BASES {PTA, PTB, PTC, PTD, PTE, PTF}
static GPIO_Type * const GPIO_InstanceTable[] = GPIO_BASES;
这里边的typedef struct {……} GPIO_Type, *GPIO_MemMapPtr;怎么理解
还有就是static GPIO_Type * const GPIO_InstanceTable[] = GPIO_BASES;等号左右表示什么意思 |