//spi_slave.v---------------------------------------
// designed for format A, active high
module SPI_slave(clk, MOSI, SSEL,datain);
input clk;
input SSEL, MOSI;
output[7:0] datain;
reg [1:0] MOSIr; always @(posedge clk) MOSIr <= {MOSIr[0], MOSI};
wire MOSI_data = MOSIr[0];
reg [3:0] bitcnt; //count for bit
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
always @(posedge clk)
begin
if((~SSEL)||(~((bitcnt<8)&&(bitcnt>0))))
bitcnt <= 4'b0000;
else
begin
bitcnt <= bitcnt + 3'b001 ;
byte_data_received <= {byte_data_received[6:0], MOSI_data};
end
end
always @(posedge clk) byte_received =(bitcnt==4'b1000);
always @(posedge clk)
if(byte_received)
begin
bitcnt <= 0;
datain <= byte_data_received; //modelsim 仿真该行报错何解 高手指点
end
endmodule
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