module TEST(clk,output_1);
input clk;
output output_1;
reg output_1;
reg[3:0] temp;
always @(posedge clk)
begin
if (temp<10)
temp<=temp+1;
else temp<=0;
end
always @(temp)
begin
if(temp==4)
output_1<=1;
else if(temp==9)
output_1<=0;
else output_1<=output_1;
end
endmodule
这个程序不知道为什么仿真就是不正确
而改成
always @(temp)
begin
if(temp<4)
output_1<=0;
else output_1<=1;
end
endmodule
就仿真真确了，为什么啊？？？？？？？？？ |
楼主
