module counter4(tb,clk,dataout,cin);
input wire tb,clk;
output reg [3:0] dataout;
output reg cin;
always @(posedge clk)
begin
if(tb==1)
begin
dataout<=0;
cin<=0;
end
else
begin
dataout<=dataout+1;
if(dataout==15)
cin<=1;
else
cin<=0;
end
end
endmodule
这个程序怎么才能实现,异步清零功能! |
楼主
