我们的MIPI CSI2 Tx 和 Rx,既可以用于ASIC上，也可以用于 FPGA上。有需要的可以和我们 sales@wwago-inc.com 联系。
MIPI CSI2 Tx
1: MIPI CSI2 transmitter for FPGA (SVT-CS4AP1-F )
key Functionality highlights include:
- 1 clock lane, one to four data lanes(configurable)
- Simple interface – legacy parallel-video input, augmented by an Early-HD signal
- Supports RAW8, RAW10, RAW12, YUV420 (legacy, 8 bit, 10 bit), YUV422 (8 bit, 10 bit), and user-defined data formats
- Optionally supports all other pixel formats, with up to 16 bit per pixel (RAW14, RGB444, RGB555, RGB565) as defined in MIPI® CSI2.
- Uses simple off-FPGA analog PHY (clock and data lane modules)
2: MIPI CSI2 transmitter for ASIC (SVT-CS4AP1 )
key Functionality highlights include:
- 1 clock lane, up to four data lanes(configurable)
- Simple interface – legacy parallel-video input, augmented by an Early-HD signal
- Supports all pixel formats, with up to 16 bit per pixel - RGB444, RGB555, RGB565, RAW8, RAW10, RAW12, RAW14, YUV420 (legacy, 8 bit, 10 bit), YUV422 (8 bit, 10 bit), and user-defined data formats.
- Uses simple analog PHY (clock and data lane modules)
- Compact solution for image sensors
3: Multiplexing MIPI CSI2 transmitter ( SVT-CS4AP2 )
key Functionality highlights include:
- One clock lane, and one to 4 data lanes (configurable)
- Up to 1.5 Gbps per lane
- Supports CSI2 RAW8, RAW10, RAW12, all YUV420, all YUV422 and User-Defined 8-bit formats (other CSI2 standards available as an option)
- Supports up to 8 concurrent video sources, for example, the sensor can send high resolution RAW12 image, where the first and last video lines contain blanking data, with embedded low resolution preview data and with embedded JPEG data
- CRC and ECC generation
- Programmable timing parameters
MIPI CSI2 Rx
1: MIPI CSI2 Receiver for FPGA (SVRPlus-CSI2-F )
key Functionality highlights include:
- Configurable (register control) number of data lanes 1 to 4 or 1 to 8, according to the state of the EIGHT_LANES compilation switch;
- Configurable (register control) 1 or 2 clock lanes when the EIGHT_LANES compilation switch is set to ON
- 64 bit internal data bus
- 1, 2 or 4 pixels output per clock, as set by the PARALLEL_PIXESL compilation switch
- Up to 1.5Gbps per lane
- All CSI2 functionality implemented in hardware, freeing the CPU to other tasks
- Support of all data formats
- Extensive set of registers, accessible by AMBA APB bus (or, optionally, by I2C)
- Programmable timing parameters
- Optional support of CSI2 compressed-video formats
- Optional output FIFO for continuous output streams
- Optional Error counting hardware, for on-line BER measurements
2: MIPI CSI2 Receiver for ASIC (SVRPlus-CSI2-I )
key Functionality highlights include:
- Configurable 1, 2, 3 or 4 data lanes (SVRPlus-CSI2-I-4X);
- Configurable 1 or 2 clock lanes; 1,2,3,4 or 8 data lanes(SVRPlus-CSI2-I-8X)
- 64 bit internal data bus for high throughput
- 1, 2 or 4 Parallel pixels output per clock
- Up to 1.5Gbps per lane
- All CSI2 functionality implemented in hardware, freeing the CPU to other tasks
- Support of all data formats
- Rich set of registers, allowing tracking of all kinds of communication errors
- Programmable timing parameters
- AMBA-APB control of all registers (I2C control optional)
- All DPHY features, except for the analog front end ,implemented by RTL
- Optional support of CSI2 compressed video formats
- Optional output FIFO for continuous output streams
- Optional Error counting , to allow on-line BER measurements
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