一个简单的CPLD程序仿真出现了问题，求教!

只看该作者 · 2017-1-14 17:03

module test02(clk,rst,count,clk_odd);
input clk,rst;
output reg [1:0]clk_odd;
output[3:0] count;
reg[3:0] count;
parameter N = 2;
always @ (posedge clk)
if(! rst)
begin
count <= 1'b0;
clk_odd <= 1'b0;
end
else
if ( count < N)
begin
count <= count + 1'b1;
end

else
case(count)
   4'b0001:
begin
clk_odd <= clk_odd + 1'b1;
end

4'b0010:
begin
count <= 1'b0;
   clk_odd <= clk_odd + 1'b1;
end
endcase
endmodule

上面的程序仿真发现无法执行 count == 1 的情况，clk_odd都是在 count == 2之后才变化，在count == 1时波形没变化，请问是哪里出问题了？
我在下面会贴出testbench代码及仿真波形

只看该作者 · 2017-1-14 17:07

下面是testbeach代码：

`timescale 100 ps/ 1 ps
module test02_vlg_tst();
// constants
// general purpose registers
//reg eachvec;
// test vector input registers
reg clk;
reg rst;
// wires
wire [1:0]clk_odd;
wire [3:0]  count;

// assign statements (if any)
test02 i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.clk_odd(clk_odd),
.count(count),
.rst(rst)
);
initial
begin
rst = 0;
clk = 0;

#200 rst = 1;
// code that executes only once
// insert code here --> begin

// --> end
//$display("Running testbench");
end
always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
#50 clk = ~clk;
// code executes for every event on sensitivity list
// insert code here --> begin

//@eachvec;
// --> end
end
endmodule