我在文件名 为uart_serial.vhd中定义了如下包集合：
library ieee;
use ieee.std_logic_1164.all;
package uart_serial is
function get_parity(get_parity_type :std_logic;
get_parity_data :std_logic_vector(7 downto 0))
return std_logic ;
end uart_serial;
package body uart_serial is
function get_patity(get_parity_type :std_logic;
get_parity_data :std_logic_vector(7 downto 0))
return std_logic is
variable tmp: std_logic :=\'1\';
variable return_value :std_logic;
begin
略。。。
if(get_parity_type =\'1\')then
return_value :=tmp;
else
return_value := not tmp;
end if;
return return_value;
end get_patity;
end uart_serial;
而在文件名为my_uart_Tx.vhd中调用了包集合中的函数get_patity，
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.uart_serial.all;
Entity my_uart_Tx is
Port(。。。略。。。
);
end my_uart_Tx;
Architecture my_uart_Tx_behavior of my_uart_Tx is
begin
。。。略
tx <=get_parity(parity_type,data_mid);
end my_uart_Tx_behavior;
编译后出现：
VHDL Subprogram Declaration error at uart_serial.vhd(4): declaration of function or procedure "get_parity" must have corresponding Subprogram Body
请问该怎么办？是不是还需做什么动作呀？ |
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